CD4504B-EP_16 [TI]
CMOS HEX VOLTAGE-LEVEL SHIFTER;
| 型号： | CD4504B-EP_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CMOS HEX VOLTAGE-LEVEL SHIFTER |
| 文件： | 总13页 (文件大小：589K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4504B-EP
www.ti.com .......................................................................................................................................................................................... SCHS369–NOVEMBER 2008
CMOS HEX VOLTAGE-LEVEL SHIFTER
FOR TTL-TO-CMOS or CMOS-TO-CMOS OPERATION
1
FEATURES
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
Independence of Power-Supply Sequence
Considerations – VCC Can Exceed VDD
Input Signals Can Exceed Both VCC and VDD
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
;
•
•
Up and Down Level-Shifting Capability
Shiftable Input Threshold for Either CMOS or
TTL Compatibility
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
•
Standardized Symmetrical Output
Characteristics
•
•
100% Tested for Quiescent Current at 20 V
Maximum Input Current of 1 µA at 18 V Over
Full Package-Temperature Range:
100 nA at 18 V and 25°C
(TOP VIEW )
16
15
14
13
12
11
10
9
VCC
AOUT
AIN
VDD
1
2
3
4
5
6
7
8
•
•
5 V, 10 V, and 15 V Parametric Ratings
FOUT
FIN
Meets All Requirements of JEDEC Standard
No. 13B, "Standard Specifications for
Description of 'B' Series CMOS Devices"
BOUT
BIN
SELECT
EOUT
EIN
COUT
CIN
DOUT
DIN
VSS
(1) Additional temperature ranges are available – contact factory
DESCRIPTION
CD4504B hex voltage level-shifter consists of six circuits which shift input signals from the VCC logic level to the
VDD logic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCC HIGH logic state.
When the SELECT input is at a LOW logic state, each circuit translates signals from one CMOS level to another.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
CD4504BMPWREP
TOP-SIDE MARKING
4504BEP
–55°C to 125°C
TSSOP – PW Reel of 2000
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CD4504B-EP
SCHS369–NOVEMBER 2008 .......................................................................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
VDD DC supply-voltage range, voltages referenced to VSS terminal
Input voltage range, all inputs
–0.5
+20
V
V
–0.5 VCC + 0.5
DC input current, any one input
±10
500
mA
mW
TA = –55°C to +100°C
TA = +100°C to +125°C
PD
Power dissipation per package
Derate Linearly at 12 mW/°C to
200 nW
Device dissipation per output transistor,
for TA = full package-temperature range (all package types)
100
mW
TA
Operating temperature range
Package thermal impedance(1)
Storage temperature range
–55
–85
+125
°C
θJA
Tstg
91.1 °C/W
+150
°C
Lead temperature (during soldering), at distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for
10 s max
+265
°C
(1) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Product Folder Link(s): CD4504B-EP
CD4504B-EP
www.ti.com .......................................................................................................................................................................................... SCHS369–NOVEMBER 2008
STATIC ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
CONDITIONS
LIMITS AT INDICATED TEMPERATURES (°C)
+25
CHARACTERISTIC
UNIT
VO
(V)
VIN
(V)
VCC
(V)
VCC
(V)
–55
–40
+85
+125
MIN
TYP
0.02
0.02
0.02
0.04
2.5
2.5
2.5
1
MAX
1.5
2
0, 5
0, 10
0, 15
0, 20
0, 5
5
5
5
5
5
5
5
5
1.5
2
1.5
2
1.5
2
1.5
2
mA
10
15
20
5
Quiescent device current,
IDD max and ICC in CMOS-CMOS mode
4
4
120
600
6
120
600
6
4
µA
20
5
20
5
20
5
Quiescent device current,
ICC max TTL-CMOS mode
0, 10
0, 15
0, 5
10
15
5
5
5
6
6
5
mA
mA
5
5
6
6
5
0.4
0.5
1.5
4.6
2.5
9.5
13.5
0.64
1.6
4.2
0.61
1.5
4
0.42
1.1
2.8
0.36
0.9
2.4
0.51
1.3
Output low (sink) current,
IOL min
0, 10
0, 15
0, 5
10
15
5
2.6
6.8
–1
3.4
–0.64 –0.61 –0.42 –0.36 –0.51
0, 5
5
–2
–1.8
–1.5
–4
–1.3 –1.15 –1.6
–3.2
–2.6
–6.8
0
Output high (source) current,
IOH min
0, 10
0, 15
0, 5
10
15
5
–1.6
–4.2
–1.1
–2.8
–0.9
–2.4
–1.3
–3.4
0.05
0.05
0.05
4.95
9.95
0.05
0.05
0.05
Output voltage:
low-level, VOL max
0, 10
0, 15
0, 5
10
15
5
0
0
4.95
9.95
5
Output voltage:
high-level, VOH min
0, 10
0, 15
10
15
10
15
10
15
15
10
15
10
15
15
18
10
14.95
0.8
0.8
1.5
1.5
3
14.95
15
TTL-CMOS
TTL-CMOS
Input low voltage,
CMOS-CMOS
VIL max(1)
1
1
5
5
0.8
0.8
1.5
1.5
3
V
1
5
CMOS-CMOS
CMOS-CMOS
TTL-CMOS
1.5
1.5
9
5
10
5
2
2
2
TTL-CMOS
Input high voltage,
CMOS-CMOS
VIH min(1)
13.5
9
5
2
5
3.5
3.5
7
3.5
3.5
7
CMOS-CMOS
13.5
13.5
5
CMOS-CMOS
10
Input current, IIN max
0, 18
±0.1
±0.1
±1
±1
±10–5
±0.1
µA
(1) Applies to the six input signals. For mode control (P13), only the CMOS-CMOS ratings apply.
Copyright © 2008, Texas Instruments Incorporated
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3
Product Folder Link(s): CD4504B-EP
CD4504B-EP
SCHS369–NOVEMBER 2008 .......................................................................................................................................................................................... www.ti.com
Figure 1. Typical Output Low (sink) Current Characteristics
Figure 2. Minimum Output Low (sink) Current Characteristics
Figure 3. Typical Output High (source) Current Characteristics
4
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): CD4504B-EP
CD4504B-EP
www.ti.com .......................................................................................................................................................................................... SCHS369–NOVEMBER 2008
Figure 4. Minimum Output High (source) Current Characteristics
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): CD4504B-EP
CD4504B-EP
SCHS369–NOVEMBER 2008 .......................................................................................................................................................................................... www.ti.com
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is always within the following
ranges:
CHARACTERISTIC
MIN
MAX
UNIT
VDD
Supply-voltage range (for TA = full package temperature range)
5
18
V
DYNAMIC ELECTRICAL CHARACTERISTICS
TA = 25°C, Input tr,tf = 20 ns, CL = 50 pF, RL = 200 Ω
LIMITS
TYP
140
VCC
(V)
VDD
(V)
CHARACTERISTIC
SHIFTING MODE
UNIT
MAX
5
5
10
15
10
15
15
5
280
280
240
240
140
550
550
140
280
280
240
240
140
400
400
120
200
100
80
TTL to CMOS
VDD > VCC
140
120
120
70
5
CMOS to CMOS
VDD > VCC
5
tPHL
Propagation delay: high-to-low,
ns
10
10
15
15
5
275
275
70
CMOS to CMOS
VCC > VDD
5
10
10
15
10
15
15
5
140
140
120
120
70
TTL to CMOS
VDD > VCC
5
5
CMOS to CMOS
VDD > VCC
5
tPLH
Propagation delay: low-to-high
ns
10
10
15
15
200
200
60
CMOS to CMOS
VCC > VDD
5
10
5
100
50
tTHL, tTLH
Transition time
All modes
10
15
ns
40
CIN
Input capacitance
Any input
5
7.5
pF
Figure 5. Quiescent Device Current
6
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): CD4504B-EP
CD4504B-EP
www.ti.com .......................................................................................................................................................................................... SCHS369–NOVEMBER 2008
Figure 6. Input Current
Figure 7. Input Voltage
Figure 8. Typical Input Switching as a Function of
High-Level Supply Voltage (SELECT at VCC – CMOS
Mode
Figure 9. Typical Input Switching as a Function of
High-Level Supply Voltage (SELECT at VSS – TTL Mode)
Copyright © 2008, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): CD4504B-EP
CD4504B-EP
SCHS369–NOVEMBER 2008 .......................................................................................................................................................................................... www.ti.com
Figure 10. High-Level Supply Voltage vs. Low-Level
Supply Voltage
A. Dimensions in parentheses are in millimeters and are derived form the basic inch dimensions as indicated. Grid
graduations are in mils (10–3 inch).
Figure 11. Dimensions and Pad Layout
8
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): CD4504B-EP
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2008
PACKAGING INFORMATION
Orderable Device
CD4504BMPWREP
V62/09606-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
PW
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4504B-EP :
Catalog: CD4504B
Military: CD4504B-MIL
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
•
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CD4504BMPWREP
TSSOP
PW
16
2000
330.0
12.4
7.0
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Nov-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 16
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 29.0
CD4504BMPWREP
2000
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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