CD54AC00F3A [TI]
军用 4 通道、2 输入、1.5V 至 5.5V 与非门 | J | 14 | -55 to 125;
| 型号： | CD54AC00F3A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 军用 4 通道、2 输入、1.5V 至 5.5V 与非门 | J | 14 | -55 to 125 栅 逻辑集成电路 触发器 |
| 文件： | 总17页 (文件大小：578K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54AC00, CD74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS303C – JANUARY 2001 – REVISED JUNE 2002
CD54AC00 . . . F PACKAGE
CD74AC00 . . . E OR M PACKAGE
(TOP VIEW)
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
1A
1B
1Y
2A
2B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
4B
4A
4Y
3B
3A
3Y
Balanced Propagation Delays
±24-mA Output Drive Current
– Fanout to 15 F Devices
2Y
GND
SCR-Latchup-Resistant CMOS Process and
Circuit Design
8
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description
The ‘AC00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function
of Y = A B or Y = A + B in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – E
Tube
Tube
CD74AC00E
CD74AC00E
CD74AC00M
CD74AC00M96
CD54AC00F3A
–55°C to 125°C
SOIC – M
CDIP – F
AC00M
Tape and reel
Tube
CD54AC00F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
H
X
L
H
L
L
H
H
X
logic diagram, each gate (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC00, CD74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS303C – JANUARY 2001 – REVISED JUNE 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
JA
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
–40°C TO
85°C
–55°C TO
125°C
T
A
= 25°C
UNIT
MIN
1.5
MAX
MIN
1.5
1.2
2.1
MAX
MIN
MAX
V
V
Supply voltage
5.5
5.5
1.5
1.2
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.5 V
= 3 V
1.2
2.1
2.1
High-level input voltage
V
V
IH
= 4.5 V
= 5.5 V
= 1.5 V
= 3 V
3.15
3.85
3.15
3.85
3.85
0.3
0.9
0.3
0.9
0.3
0.9
V
IL
Low-level input voltage
= 4.5 V
= 5.5 V
1.35
1.65
1.35
1.65
1.65
V
V
Input voltage
0
0
V
V
0
0
V
0
0
V
V
V
V
I
CC
CC
CC
Output voltage
V
CC
O
CC
CC
I
I
High-level output current
Low-level output current
V
CC
V
CC
V
CC
V
CC
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
= 1.5 V to 3 V
–24
24
–24
24
–24
24
mA
mA
OH
OL
50
50
50
∆t/∆v Input transition rise or fall rate
ns/V
= 3.6 V to 5.5 V
20
20
20
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC00, CD74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS303C – JANUARY 2001 – REVISED JUNE 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
–40°C TO
85°C
–55°C TO
125°C
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
1.4
MAX
MIN
1.4
MAX
MIN
1.4
MAX
1.5 V
3 V
I
= –50 µA
2.9
2.9
2.9
OH
4.5 V
3 V
4.4
4.4
4.4
V
OH
V = V or V
I IH
I
I
I
I
= –4 mA
2.58
3.94
2.48
3.8
2.4
V
IL
OH
OH
OH
OH
= –24 mA
= –50 mA
= –75 mA
4.5 V
5.5 V
5.5 V
1.5 V
3 V
3.7
†
†
3.85
3.85
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 µA
OL
4.5 V
3 V
0.1
0.1
0.1
V
OL
V = V or V
I
I
I
I
= 12 mA
= 24 mA
0.36
0.36
0.44
0.44
0.5
V
I
IH
IL
OL
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
0.5
†
= 50 mA
= 75 mA
1.65
†
1.65
±1
I
I
V = V
or GND
or GND,
±0.1
4
±1
80
10
µA
µA
pF
I
I
CC
CC
V = V
I
O
= 0
40
CC
I
C
10
10
i
†
Testoneoutputatatime, notexceeding1-secondduration. Measurementismadebyforcingindicatedcurrentandmeasuringvoltagetominimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
switching characteristics over recommended operating free-air temperature range,
= 1.5 V, C = 50 pF (unless otherwise noted) (see Figure 1)
V
CC
L
–40°C TO
85°C
–55°C TO
125°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
83
83
91
91
PLH
A or B
Y
ns
PHL
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V, C = 50 pF (unless otherwise noted) (see Figure 1)
V
CC
L
–40°C TO
85°C
–55°C TO
125°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
2.7
MAX
MIN
2.6
MAX
10.2
10.2
t
t
9.3
9.3
PLH
A or B
Y
ns
2.7
2.6
PHL
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC00, CD74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS303C – JANUARY 2001 – REVISED JUNE 2002
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V, C = 50 pF (unless otherwise noted) (see Figure 1)
CC
L
–40°C TO
85°C
–55°C TO
125°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.9
MAX
MIN
1.8
MAX
t
t
6.6
6.6
7.3
7.3
PLH
A or B
Y
ns
1.9
1.8
PHL
operating characteristics, V
= 5 V, T = 25°C
CC
A
PARAMETER
TYP
UNIT
C
Power dissipation capacitance
45
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC00, CD74AC00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS303C – JANUARY 2001 – REVISED JUNE 2002
PARAMETER MEASUREMENT INFORMATION
2 × V
TEST
S1
CC
Open
GND
S1
†
R1 = 500 Ω
t
/t
Open
PLH PHL
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
†
L
R2 = 500 Ω
(see Note A)
t
w
V
CC
†
When V
= 1.5 V, R1 = R2 = 1 kΩ
CC
Input
50% V
50% V
CC
CC
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
V
CC
Reference
Input
V
CC
50% V
CC
CLR
Input
50% V
CC
0 V
0 V
t
t
h
su
t
rec
V
CC
CC
0 V
Data
Input
90%
90%
V
CC
50%
10%
50% V
10%
50% V
CC
CLK
t
t
f
0 V
r
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
V
CC
V
CC
Input
50% V
50% V
CC
CC
Output
Control
50% V
50% V
CC
CC
0 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
In-Phase
Output
Output
Waveform 1
90%
≈V
CC
50%
10%
50% V
10%
CC
V
50% V
20% V
CC
CC
S1 at 2 × V
(see Note B)
OL
CC
V
OL
t
t
f
r
t
t
PHL
90%
PLH
t
t
PHZ
PZH
V
V
OH
Output
Waveform 2
S1 at GND
90%
Out-of-Phase
Output
50% V
10%
50%
10%
V
OH
CC
80% V
50% V
CC
OL
CC
t
f
t
≈0 V
r
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
Phase relationships between waveforms are arbitrary.
D. For clock inputs, f is measured with the input duty cycle at 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
pd
PLH
PZL
PLZ
PHL
PZH
PHZ
are the same as t
are the same as t
.
en
dis
.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CD54AC00F3A
ACTIVE
CDIP
J
14
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
CD54AC00F3A
Samples
CD74AC00E
ACTIVE
ACTIVE
PDIP
SOIC
N
D
14
14
25
RoHS & Green
NIPDAU
NIPDAU
N / A for Pkg Type
-55 to 125
-55 to 125
CD74AC00E
AC00M
Samples
Samples
CD74AC00M96
2500 RoHS & Green
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-May-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54AC00, CD74AC00 :
Catalog : CD74AC00
•
Military : CD54AC00
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74AC00M96
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 14
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
CD74AC00M96
D
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
CD74AC00E
CD74AC00E
N
N
PDIP
PDIP
14
14
25
25
506
506
13.97
13.97
11230
11230
4.32
4.32
Pack Materials-Page 3
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
S
C
A
L
E
0
.
9
0
0
CERAMIC DUAL IN LINE PACKAGE
4X .005 MIN
[0.13]
PIN 1 ID
(OPTIONAL)
A
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
.13 MIN TYP
[3.3]
SEATING PLANE
C
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL B
14
SEE DETAIL A
1
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
(
.063)
[1.6]
SOLDER MASK
OPENING
METAL
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
(R.002 ) TYP
[0.05]
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
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