CD54AC161F3A [TI]
4-BIT SYNCHRONOUS BINARY COUNTERS; 4位同步二进制计数器
| 型号： | CD54AC161F3A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-BIT SYNCHRONOUS BINARY COUNTERS |
| 文件： | 总15页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
CD54AC161 . . . F PACKAGE
CD74AC161 . . . E OR M PACKAGE
(TOP VIEW)
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
CLR
CLK
A
V
CC
RCO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Synchronously Programmable
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Q
A
B
Q
B
Exceeds 2-kV ESD Protection per
MIL-STD-883, Method 3015
C
Q
C
D
Q
D
ENP
GND
ENT
LOAD
description/ordering information
The ’AC161 devices are 4-bit binary counters.
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting These devices are fully programmable; that is, they can be preset to any number between
0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the
enable inputs.
The clear function is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low,
regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15, with Q high). This high-level overflow ripple-carry pulse
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – E
Tube
Tube
CD74AC161E
CD74AC161E
CD74AC161M
CD74AC161M96
CD54AC161F3A
–55°C to 125°C
SOIC – M
CDIP – F
AC161M
Tape and reel
Tube
CD54AC161F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
FUNCTION TABLE
INPUTS
OUTPUTS
Q RCO
n
FUNCTION
Reset (clear)
Parallel load
CLR
L
CLK
ENP
ENT
LOAD
A,B,C,D
X
↑
X
X
X
h
l
X
X
X
h
X
l
X
l
X
l
L
L
L
H
L
H
H
↑
l
h
X
X
X
Note 1
H
↑
h
h
h
Count
Note 1 Count
H
X
X
q
q
Note 1
Inhibit
L
n
H
X
n
H = high level, L = low level, X = don’t care, h = high level one setup time prior to the CLK
low-to-high transition, l = low level one setup time prior to the CLK low-to-high transition, q = the
state of the referenced output prior to the CLK low-to-high transition, and ↑ = CLK low-to-high
transition.
NOTE 1: The RCO output is high when ENT is high and the counter is at terminal count
(HHHH).
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
logic diagram (positive logic)
9
LOAD
10
ENT
15
RCO
†
LD
7
ENP
†
CK
2
CLK
CK
LD
1
CLR
R
M1
G2
1, 2T/1C3
14
13
Q
Q
A
B
G4
3D
4R
3
A
M1
G2
1, 2T/1C3
G4
3D
4R
4
B
M1
G2
1, 2T/1C3
12
Q
C
G4
3D
4R
5
C
M1
G2
1, 2T/1C3
11
Q
D
G4
3D
4R
6
D
†
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
logic symbol, each D/T flip-flop
LD (Load)
M1
G2
1, 2T/1C3
TE (Toggle Enable)
CK (Clock)
Q (Output)
G4
3D
4R
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
†
TG
TG
LD
TG
Q
TG
†
LD
†
CK
D
R
†
CK
TG
TG
†
†
CK
CK
†
The origins of LD and CK are shown in the logic diagram of the overall device.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (asynchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Preset
Async
Clear
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
I
Input clamp current, I (V < 0 V or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 V or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V > 0 V or V < V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
O
O
CC
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
JA
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
–55°C to
125°C
–40°C to
85°C
T
A
= 25°C
UNIT
MIN
1.5
MAX
MIN
1.5
MAX
MIN
MAX
V
V
Supply voltage
5.5
5.5
1.5
1.2
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.5 V
= 3 V
1.2
1.2
High-level input voltage
2.1
2.1
2.1
V
V
IH
= 5.5 V
= 1.5 V
= 3 V
3.85
3.85
3.85
0.3
0.9
0.3
0.9
0.3
0.9
V
IL
Low-level input voltage
= 5.5 V
1.65
1.65
1.65
V
V
Input voltage
0
0
V
V
0
0
V
0
0
V
V
V
V
I
CC
CC
CC
Output voltage
V
CC
O
CC
CC
I
High-level output current
Low-level output current
–24
24
–24
24
–24
24
mA
mA
OH
OL
I
V
V
= 1.5 V to 3 V
50
50
50
CC
∆t/∆v
Input transition rise or fall rate
ns
= 3.6 V to 5.5 V
20
20
20
CC
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
–55°C to
125°C
–40°C to
85°C
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
1.4
2.9
4.4
2.58
3.94
–
MAX
MIN
1.4
2.9
4.4
2.4
3.7
3.85
–
MAX
MIN
1.4
2.9
4.4
2.48
3.8
–
MAX
1.5 V
3 V
I
= –50 µA
OH
4.5 V
3 V
V
OH
V = V or V
IH
I
I
I
I
= –4 mA
V
I
IL
OH
OH
OH
OH
= –24 mA
= –50 mA
= –75 mA
4.5 V
5.5 V
5.5 V
1.5 V
3 V
†
†
–
3.85
0.1
0.1
0.1
0.36
0.36
–
0.1
0.1
0.1
0.5
0.5
1.65
–
0.1
0.1
0.1
0.44
0.44
–
I
= 50 µA
OL
4.5 V
3 V
V
OL
V = V or V
I
I
I
I
= 12 mA
= 24 mA
V
I
IH
IL
OL
OL
OL
OL
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
†
= 50 mA
= 75 mA
†
–
1.65
±1
I
I
V = V
or GND
or GND,
±0.1
8
±1
µA
µA
pF
I
I
CC
CC
V = V
I
I
O
= 0
160
10
80
CC
C
10
10
i
†
Testoneoutputatatime, notexceeding1-secondduration. Measurementismadebyforcingindicatedcurrentandmeasuringvoltagetominimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
–55°C to
125°C
–40°C to
85°C
V
CC
UNIT
MIN
MAX
MIN
MAX
1.5 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
7
64
90
8
73
f
Clock frequency
Pulse duration
MHz
clock
103
69
7.7
5.5
63
7
61
6.8
4.8
55
6.1
4.4
55
6.1
4.4
66
7.4
5.3
0
CLK high or low
CLR low
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
t
w
ns
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
5
63
7
A, B, C, or D
LOAD
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
5
t
su
Setup time, before CLK↑
ns
75
8.4
6
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
0
A, B, C, or D
ENP or ENT
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
0
0
0
0
t
t
Hold time, after CLK↑
ns
ns
h
0
0
3.3 V ± 0.3 V
5 V ± 0.5 V
0
0
0
0
1.5 V
75
8.4
6
66
7.4
5.3
Recovery time, CLR↑ before CLK↑
3.3 V ± 0.3 V
5 V ± 0.5 V
rec
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
–55°C to
125°C
–40°C to
85°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
7
MAX
MIN
8
MAX
1.5 V
f
max
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
64
90
–
73
103
–
MHz
209
23.4
16.7
207
190
21
RCO
Any Q
RCO
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
6
6
4.3
–
4.3
–
15.2
188
21
CLK
ENT
CLR
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
5.9
4.2
–
23.1
16.5
129
5.9
4.2
–
15
117
13.1
9.4
188
21
t
pd
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
3.6
2.6
–
14.4
10.3
207
3.7
2.7
–
ns
Any Q
RCO
3.3 V ± 0.3 V
5 V ± 0.5 V
1.5 V
5.9
4.2
–
23.1
16.5
207
5.9
4.2
–
15
188
21
3.3 V ± 0.3 V
5 V ± 0.5 V
5.9
4.2
23.1
16.5
5.9
4.2
15
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
66
pF
pd
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54AC161, CD74AC161
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
R1 = 500 Ω
R2 = 500 Ω
t
/t
Open
PLH PHL
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
(see Note A)
t
w
V
CC
NOTE: When V
= 1.5 V, R1 and R2 = 1 kΩ.
CC
50% V
50% V
CC
Input
CC
LOAD CIRCUIT
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
V
V
CC
CC
Reference
Input
CLR
Input
50% V
50% V
CC
CC
0 V
0 V
t
t
h
su
t
rec
V
V
CC
CC
Data
Input
90%
90%
50% V
50%
10%
50% V
10%
CLK
CC
CC
0 V
0 V
t
t
f
r
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
V
CC
V
CC
Input
50% V
50% V
CC
CC
PHL
90%
Output
Control
50% V
50% V
CC
CC
0 V
0 V
t
t
PLH
t
t
PLZ
PZL
V
OH
CC
In-Phase
Output
Output
Waveform 1
90%
t
≈V
CC
50%
10%
50% V
10%
50% V
CC
CC
V
V
V
+ 0.3 V
OL
OL
S1 at 2 × V
(see Note B)
CC
t
f
r
V
OL
t
t
PLH
PHL
90%
t
t
PZH
PHZ
V
V
OH
90%
Output
Waveform 2
S1 at Open
(see Note B)
Out-of-Phase
Output
V
OH
50% V
10%
50%
10%
CC
– 0.3 V
OH
50% V
OL
t
t
≈0 V
f
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
Phase relationships between waveforms are arbitrary.
D. For clock inputs, f is measured with the input duty cycle at 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
pd
PLH
PZL
PLZ
PHL
PZH
PHZ
are the same as t
are the same as t
.
en
dis
.
I. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
PDIP
Drawing
CD54AC161F3A
CD74AC161E
ACTIVE
ACTIVE
J
16
16
1
TBD
A42 SNPB
N / A for Pkg Type
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74AC161EE4
CD74AC161M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
N
D
D
D
D
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74AC161M96
CD74AC161M96E4
CD74AC161ME4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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www.ti.com/audio
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www.ti.com/automotive
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dsp.ti.com
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Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Low Power Wireless www.ti.com/lpw
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
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