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CD54HC11_14 [TI]

High-Speed CMOS Logic Triple 3-Input AND Gate;
CD54HC11_14
型号： CD54HC11_14
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

High-Speed CMOS Logic Triple 3-Input AND Gate

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CD54/74HC11,  
CD54/74HCT11  
Data sheet acquired from Harris Semiconductor  
SCHS273A  
High Speed CMOS Logic  
Triple 3-Input AND Gate  
August 1997 - Revised May 2000  
Features  
Description  
• Buffered Inputs  
The ’HC11 and ’HCT11 logic gates utilize silicon gate CMOS  
technology to achieve operating speeds similar to LSTTL  
gates with the low power consumption of standard CMOS  
integrated circuits. All devices have the ability to drive 10  
LSTTL loads. The HCT logic family is functionally pin  
compatible with the standard LS logic family.  
• Typical Propagation Delay: 8ns at V  
o
= 5V,  
[ /Title  
(CD54  
HCT11  
,
CD74  
HC11,  
CD74  
HCT11  
)
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
Ordering Information  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
TEMP. RANGE  
o
PART NUMBER  
CD54HC11F  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
/Sub-  
ject  
(High  
CD54HC11F3A  
CD74HC11E  
CD74HC11M  
CD54HCT11F  
CD54HCT11F3A  
CD74HCT11E  
CD74HCT11M  
NOTES:  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
14 Ld SOIC  
at V  
= 5V  
CC  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
14 Ld SOIC  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
2. Die for this part number is available which meets all electrical  
specifications. Please contact your local TI sales office or cus-  
tomer service for ordering information.  
Pinout  
CD54HC11, CD54HCT11  
(CERDIP)  
CD54HCT11, CD74HC11, CD74HCT11  
(PDIP, SOIC)  
TOP VIEW  
1A  
1B  
1
2
3
4
5
6
7
14 V  
CC  
13 1C  
12 1Y  
11 3C  
10 3B  
2A  
2B  
2C  
2Y  
9
8
3A  
3Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2000, Texas Instruments Incorporated  
1
CD54/74HC11, CD54/74HCT11  
Functional Diagram  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
V
1A  
1B  
CC  
1C  
1Y  
3C  
3B  
3A  
3Y  
2A  
2B  
2C  
2Y  
8
GND  
TRUTH TABLE  
INPUTS  
OUTPUT  
nA  
L
nB  
L
nC  
nY  
L
L
H
L
L
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
L
L
H
L
L
H
H
L
H
H
Logic Symbol  
nA  
nB  
nC  
nY  
2
CD54/74HC11, CD54/74HCT11  
Absolute Maximum Ratings  
Thermal Information  
o
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Thermal Resistance (Typical, Note 3)  
θ
( C/W)  
θ
( C/W)  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
JA  
JC  
PDIP Package . . . . . . . . . . . . . . . . . . .  
CERDIP Package . . . . . . . . . . . . . . . .  
SOIC Package. . . . . . . . . . . . . . . . . . .  
100  
130  
180  
N/A  
55  
N/A  
IK  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
DC Output Diode Current, I  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
O
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
O
o
o
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
o
DC V  
or Ground Current, I  
I
. . . . . . . . . . . . . . . . . .±50mA  
CC  
CC or GND  
(SOIC - Lead Tips Only)  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
3. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
HC TYPES  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
High Level Input  
Voltage  
V
-
-
-
2
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
4.5  
3.15  
-
-
3.15  
-
-
3.15  
6
2
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
-0.02  
2
1.9  
1.9  
1.9  
OH  
IH  
V
IL  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
V
V
or  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
IH  
V
IL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
3
CD54/74HC11, CD54/74HCT11  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
2
-
20  
-
40  
µA  
CC  
CC  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage CMOS Loads  
V
V
or  
IH  
-0.02  
4.5  
4.4  
3.98  
4.4  
3.84  
4.4  
3.7  
OH  
V
IL  
High Level Output  
Voltage  
-4  
4.5  
-
-
-
TTL Loads  
Low Level Output  
Voltage  
CMOS Loads  
V
V
V
or  
IH  
0.02  
4.5  
4.5  
5.5  
5.5  
-
-
-
-
-
0.1  
-
-
-
0.1  
0.33  
±1  
-
-
-
0.1  
0.4  
±1  
V
V
OL  
IL  
Low Level Output  
Voltage  
TTL Loads  
4
-
0.26  
±0.1  
Input Leakage  
Current  
I
V
and  
GND  
µA  
I
CC  
Quiescent Device  
Current  
I
V
or  
-
-
-
-
-
2
-
-
20  
-
-
40  
µA  
µA  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
(Note 4)  
∆I  
CC  
V
4.5 to  
5.5  
100  
360  
450  
490  
CC  
- 2.1  
NOTE:  
4. For dual-supply systems theorectical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
All  
UNIT LOADS  
0.5  
NOTE: Unit Load is ∆I  
Specifications table, e.g. 360µA max at 25 C.  
limit specified in DC Electrical  
o
CC  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
Propagation Delay,  
Input to Output (Figure 1)  
t
, t  
PLH PHL  
C = 50pF  
2
4.5  
6
-
-
-
-
-
-
100  
20  
17  
-
-
-
-
-
125  
25  
21  
-
-
-
-
-
150  
30  
26  
-
ns  
ns  
ns  
ns  
L
-
Propagation Delay, Data Input to  
Output Y  
t , t  
PLH PHL  
C = 15pF  
5
8
L
4
CD54/74HC11, CD54/74HCT11  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
95  
19  
16  
10  
-
MIN  
MAX  
110  
22  
UNITS  
ns  
Transition Times (Figure 1)  
t
, t  
TLH THL  
C = 50pF  
2
4.5  
6
-
-
-
-
-
-
-
75  
15  
13  
10  
-
-
-
-
-
-
-
-
-
-
-
L
ns  
-
19  
ns  
Input Capacitance  
C
C = 50pF  
-
-
10  
pF  
I
L
Power Dissipation Capacitance  
(Notes 5, 6)  
C
C = 15pF  
5
26  
-
pF  
PD  
L
HCT TYPES  
Propagation Delay, Input to  
Output (Figure 2)  
t
, t  
PLH PHL  
C = 50pF  
4.5  
5
-
-
-
28  
-
-
-
35  
-
-
-
42  
-
ns  
ns  
L
Propagation Delay, Data Input to  
Output Y  
t , t  
PLH PHL  
C = 15pF  
11  
L
Transition Times (Figure 2)  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
4.5  
-
-
-
-
-
-
15  
10  
-
-
-
-
19  
10  
-
-
-
-
22  
10  
-
ns  
pF  
pF  
L
C
C = 50pF  
L
I
Power Dissipation Capacitance  
(Notes 5, 6)  
C
-
5
28  
PD  
NOTES:  
5. C  
is used to determine the dynamic power consumption, per gate.  
2
PD  
6. P = V  
f (C  
PD  
+ C ) where f = input frequency, C = output load capacitance, V = supply voltage.  
CC  
D
CC  
i
L
i
L
Test Circuits and Waveforms  
t = 6ns  
f
t = 6ns  
t = 6ns  
t = 6ns  
r
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
5
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
Customers are responsible for their applications using TI components.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
semiconductor products or services might be or are used. TI’s publication of information regarding any third  
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 2000, Texas Instruments Incorporated  

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