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CD54HC14 [TI]

High-Speed CMOS Logic Hex Inverting Schmitt Trigger; 高速CMOS逻辑六角反相施密特触发器
CD54HC14
型号： CD54HC14
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

High-Speed CMOS Logic Hex Inverting Schmitt Trigger
高速CMOS逻辑六角反相施密特触发器

触发器
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中文：  中文翻译
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CD54HC14, CD74HC14,  
CD54HCT14, CD74HCT14  
Data sheet acquired from Harris Semiconductor  
SCHS129E  
High-Speed CMOS Logic  
Hex Inverting Schmitt Trigger  
January 1998 - Revised July 2004  
Features  
Description  
• Unlimited Input Rise and Fall Times  
• Exceptionally High Noise Immunity  
The ’HC14 and ’HCT14 each contain six inverting Schmitt  
triggers in one package.  
[ /Title  
(CD74H  
C14,  
CD74H  
CT14)  
/Subject  
(High  
Speed  
CMOS  
Logic  
Ordering Information  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
TEMP. RANGE  
o
PART NUMBER  
CD54HC14F3A  
CD54HCT14F3A  
CD74HC14E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
CD74HC14M  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld PDIP  
• HC Types  
CD74HC14MT  
CD74HC14M96  
CD74HC14PW  
CD74HC14PWR  
CD74HCT14E  
- 2V to 6V Operation  
Hex  
Invert-  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
CD74HCT14M  
CD74HCT14MT  
CD74HCT14M96  
CD74HCT14PW  
CD74HCT14PWR  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld TSSOP  
14 Ld TSSOP  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
Pinout  
CD54HC14, CD54HCT14  
(CERDIP)  
CD74HC14, CD74HCT14  
(PDIP, SOIC, TSSOP)  
TOP VIEW  
1A  
1Y  
1
2
3
4
5
6
7
14 V  
CC  
13 6A  
12 6Y  
11 5A  
10 5Y  
2A  
2Y  
3A  
3Y  
9
8
4A  
4Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2004, Texas Instruments Incorporated  
1
CD54HC14, CD74HC14, CD54HCT14, CD74HCT14  
Functional Diagram  
2
1
3
1A  
2A  
3A  
4A  
5A  
6A  
1Y  
2Y  
3Y  
4Y  
5Y  
6Y  
4
6
5
8
9
11  
13  
10  
12  
GND = 7  
V
= 14  
CC  
TRUTH TABLE  
INPUT (A)  
OUTPUT (Y)  
L
H
L
H
H= High Level  
L= Low Level  
Logic Diagram  
nA  
nY  
V
H
V
O
V
= V + - V -  
T T  
H
V
I
V - V +  
T
T
V +  
V -  
T
T
V
CC  
V
V
H
I
GND  
V
CC  
V
O
GND  
FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP  
2
CD54HC14, CD74HC14, CD54HCT, CD74HCT14  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
JA  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86  
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113  
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
IK  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
DC Output Diode Current, I  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Drain Current, per Output, I  
O
o
o
For -0.5V < V < V  
+0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
O
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
(SOIC - Lead Tips Only)  
O
O
CC  
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA  
CC  
CC  
Operating Conditions  
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
CC  
I
O
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
HC TYPES  
SYMBOL V (V)  
I
(mA)  
V
(V)  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Input Switch Points  
V +  
-
-
-
-
2
0.7  
1.7  
2.1  
0.3  
0.9  
1.2  
0.2  
0.4  
0.6  
1.9  
4.4  
5.9  
-
1.5  
3.15  
4.2  
1.0  
2.2  
3.0  
1.0  
1.4  
1.6  
-
0.7  
1.7  
2.1  
0.3  
0.9  
1.2  
0.2  
0.4  
0.6  
1.9  
4.4  
5.9  
-
1.5  
3.15  
4.2  
1.0  
2.2  
3.0  
1.0  
1.4  
1.6  
-
0.7  
1.7  
2.1  
0.3  
0.9  
1.2  
0.2  
0.4  
0.6  
1.9  
4.4  
5.9  
-
1.5  
3.15  
4.2  
1.0  
2.2  
3.0  
1.0  
1.4  
1.6  
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
T
4.5  
6
2
V -  
-
-
T
4.5  
6
V
2
H
4.5  
6
High Level Output  
Voltage CMOS Loads  
V
V - or  
-0.02  
2
OH  
T
V +  
T
-0.02  
-0.02  
-
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage TTL Loads  
-
-
-
-
-4  
4.5  
6
3.98  
5.48  
-
-
3.84  
5.34  
-
-
3.7  
5.2  
-
-
-5.2  
0.02  
0.02  
0.02  
-
-
-
-
LowLevelOutputVoltage  
CMOS Loads  
V
V
or  
IH  
2
0.1  
0.1  
0.1  
-
0.1  
0.1  
0.1  
-
0.1  
0.1  
0.1  
-
OL  
V
IL  
4.5  
6
-
-
-
-
-
-
Low Level Output Voltage  
TTL Loads  
-
-
-
-
4
4.5  
6
-
0.26  
0.26  
-
0.33  
0.33  
-
0.4  
0.4  
5.2  
-
-
-
3
CD54HC14, CD74HC14, CD54HCT14, CD74HCT14  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
SYMBOL V (V)  
I
(mA)  
V
(V)  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Input Leakage Current  
I
V
or  
-
6
-
±0.1  
-
±1  
-
±1  
µA  
I
CC  
GND  
Quiescent Device  
Current  
I
V
GND  
or  
0
-
6
-
2
-
20  
-
40  
µA  
CC  
CC  
HCT TYPES  
Input Switch Points  
V +  
-
4.5  
1.2  
1.4  
0.5  
0.6  
0.4  
0.4  
4.4  
1.9  
2.1  
1.2  
1.4  
1.4  
1.5  
-
1.2  
1.4  
0.5  
0.6  
0.4  
0.4  
4.4  
1.9  
2.1  
1.2  
1.4  
1.4  
1.5  
-
1.2  
1.4  
0.5  
0.6  
0.4  
0.4  
4.4  
1.9  
2.1  
1.2  
1.4  
1.4  
1.5  
-
V
V
V
V
V
V
V
T
5.5  
4.5  
5.5  
4.5  
5.5  
4.5  
V -  
T
V
H
High Level Output  
V
V
or  
IH  
-0.02  
OH  
Voltage CMOS Loads  
V
IL  
High Level Output  
Voltage TTL Loads  
-4  
4.5  
4.5  
4.5  
5.5  
3.98  
-
3.84  
-
3.7  
-
V
V
LowLevelOutputVoltage  
CMOS Loads  
V
V
V
or  
IH  
0.02  
-
-
-
0.1  
-
-
-
0.1  
0.33  
±1  
-
-
-
0.1  
0.4  
±1  
OL  
IL  
Low Level Output Voltage  
TTL Loads  
4
-
0.26  
±0.1  
V
Input Leakage Current  
I
V
µA  
I
CC  
and  
GND  
Quiescent Device  
Current  
I
V
GND  
or  
0
-
5.5  
-
-
2
-
-
20  
-
-
40  
µA  
µA  
CC  
CC  
Additional Quiescent  
Device Current Per Input (Note 2)  
∆I  
CC  
V
4.5 to  
5.5  
360  
450  
490  
CC  
- 2.1  
Pin: 1 Unit Load  
NOTE:  
2. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
nA  
UNIT LOADS  
0.6  
NOTE: Unit Load is ∆I  
tions table, e.g., 360µA max at 25 C.  
limit specified in DC Electrical Specifica-  
CC  
o
4
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
Propagation Delay,  
A to Y  
t
, t  
C = 50pF  
2
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
135  
27  
-
-
-
-
-
-
-
-
-
-
170  
34  
-
-
-
205  
41  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
pF  
PLH PHL  
L
C = 50pF  
L
C = 15pF  
11  
-
-
L
C = 50pF  
6
23  
75  
15  
13  
10  
-
29  
95  
19  
16  
10  
-
-
35  
110  
22  
19  
10  
-
L
Output Transition Times  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
L
2
-
18  
-
4.5  
6
-
-
-
C
-
-
-
-
-
I
Power Dissipation Capacitance  
(Notes 3, 4)  
C
5
20  
-
PD  
HCT TYPES  
Propagation Delay,  
A to Y  
t
, t  
C = 50pF  
4.5  
5
-
-
-
-
-
-
16  
-
38  
-
-
-
-
-
-
48  
-
-
-
-
-
-
57  
-
ns  
ns  
ns  
pF  
pF  
PLH PHL  
L
C = 15pF  
L
Output Transition Times  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
L
4.5  
-
15  
10  
-
19  
10  
-
22  
10  
-
C
-
-
-
I
Power Dissipation Capacitance  
(Notes 3, 4)  
C
5
20  
PD  
NOTES:  
3. C  
is used to determine the dynamic power consumption, per inverter.  
2
PD  
4. P = V  
f (C  
PD  
+ C ) where f = input frequency, C = output load capacitance, V = supply voltage.  
CC  
D
CC  
i
L
i
L
Test Circuits and Waveforms  
t = 6ns  
f
t = 6ns  
t = 6ns  
t = 6ns  
r
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 4. HC TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
5
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Feb-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
CDIP  
CDIP  
PDIP  
Drawing  
CD54HC14F  
CD54HC14F3A  
CD54HCT14F  
CD54HCT14F3A  
CD74HC14E  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
14  
14  
14  
14  
14  
1
1
None  
None  
None  
None  
Call TI  
Call TI  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
J
1
J
1
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD74HC14M  
CD74HC14M96  
CD74HC14MT  
CD74HC14PW  
CD74HC14PWR  
CD74HCT14E  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
D
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
50  
2500  
250  
90  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
SOIC  
D
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
TSSOP  
TSSOP  
PDIP  
PW  
PW  
N
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-1-250C-UNLIM  
CU NIPDAU Level-NC-NC-NC  
2000  
25  
Pb-Free  
(RoHS)  
Pb-Free  
(RoHS)  
CD74HCT14M  
CD74HCT14M96  
CD74HCT14MT  
CD74HCT14PW  
CD74HCT14PWR  
SOIC  
D
50  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
SOIC  
D
2500  
250  
90  
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
SOIC  
D
Pb-Free  
(RoHS)  
CU NIPDAU Level-2-260C-1 YEAR/  
Level-1-235C-UNLIM  
TSSOP  
TSSOP  
PW  
PW  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-250C-UNLIM  
2000  
Pb-Free  
(RoHS)  
CU NIPDAU Level-1-250C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional  
product content details.  
None: Not yet available Lead (Pb-Free).  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,  
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-Feb-2005  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°–8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
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