CD54HC160F [TI]
BCD SYNCHRONOUS DECADE COUNTERS; BCD同步十进制计数器
| 型号： | CD54HC160F |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BCD SYNCHRONOUS DECADE COUNTERS |
| 文件： | 总14页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
CD54HC160, CD54HC162 . . . F PACKAGE
(TOP VIEW)
Synchronous Counting and Loading
Two Count-Enable Inputs for n-Bit
Cascading
CLR
CLK
A
V
CC
RCO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Asynchronous Reset (CD54HC160)
Synchronous Reset (CD54HC162)
Q
A
B
Q
B
Look-Ahead Carry for High-Speed Counting
C
Q
C
Operating Range 2-V to 6-V V
CC
D
Q
D
EPIC (Enhanced-Performance Implanted
CMOS) Process
ENP
GND
ENT
LOAD
Packaged in Ceramic (F) DIPs
description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. The CD54HC160 and CD54HC162 are BCD decade counters. Synchronous operation is
provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other
when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation
eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters.
A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the CD54HC160 is asynchronous. A low level at the clear (CLR) input sets all four of the
flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 with Q high). This high-level overflow ripple-carry pulse can
A
be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level
of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The CD54HC160 and CD54HC162 are supplied in 16-lead hermetic dual-in-line ceramic packages (F suffix),
and are characterized for operation over the full military temperature range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
†
logic symbol
CD54HC160 BINARY COUNTER
WITH DIRECT CLEAR
CTRDIV10
CT=0
1
9
CLR
LOAD
M1
15
M2
3CT=9
RCO
10
ENT
G3
7
2
ENP
CLK
G4
C5/2,3,4+
3
4
5
6
14
13
12
11
[1]
[2]
[4]
[8]
Q
A
A
B
C
D
1,5D
Q
B
Q
C
Q
D
CD54HC162 BINARY COUNTER
WITH SYNCHRONOUS CLEAR
CTRDIV10
5CT=0
1
CLR
9
LOAD
M1
15
M2
3CT=9
RCO
10
ENT
G3
7
2
ENP
CLK
G4
C5/2,3,4+
3
4
5
6
14
13
12
11
[1]
[2]
[4]
[8]
Q
A
A
B
C
D
1,5D
Q
B
Q
C
Q
D
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
†
CD54HC160 logic diagram (positive logic)
1
CLR
9
LOAD
10
ENT
15
RCO
7
ENP
2
CLK
14
Q
C1
1D
A
R
3
A
13
C1
Q
B
1D
R
4
B
12
Q
C1
C
1D
R
5
C
11
C1
Q
D
1D
R
6
D
†
CD54HC162 decade counter is similar; however, the clear is synchronous.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
logic diagram, each D/T flip-flop (positive logic)
ENT
Q
Q
CL
p
LOAD
n
n
CL
p
CL
p
†
CLR
CL
p
n
n
n
p
CL
CL
CL
p
n
CL CL
†
CLR
D
CL
CLK
†
Connect to V
for CD54HC162.
DD
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
typical clear, preset, count, and inhibit sequences
Illustrated below is the following sequence:
1. Clear outputs to zero (CD54HC160 is asynchronous; CD54HC162 is synchronous)
2. Preset BCD to seven
3. Count to eight, nine, zero, one, two, and three
4. Inhibit
CD54HC160, CD54HC162
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
Q
Q
A
B
C
Outputs
Q
D
RCO
7
8
9
0
1
2
3
Count
Inhibit
Sync Preset
Clear
Async
Clear
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < –0.5 V or V > V + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
O
Output clamp current, I
(V < –0.5 V or V > V
+ 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
CC
OK
O
Continuous output current, I (V = –0.5 V to V
Continuous current through V
+ 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
CC
Power dissipation, P (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
D
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265°C
Lead temperature, unit inserted into a PC board (minimum thickness 1,6 mm, 1/16 inch)
with solder contacting lead tips only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 100°C, derate linearly at a factor of 8 mW/°C.
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
Supply voltage
2
1.5
6
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
V
High-level input voltage
= 4.5 V
= 6 V
3.15
4.2
V
V
= 2 V
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
V
V
Input voltage
0
0
V
V
V
V
I
CC
Output voltage
O
CC
V
CC
V
CC
V
CC
= 2 V
0
1000
500
400
125
t , t
r f
Input transition rise or fall times
Operating free-air temperature
= 4.5 V
= 6 V
0
ns
0
T
A
–55
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CD54HC160
CD54HC162
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
1.9
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
2 V
4.5 V
6 V
I
= –20
A
4.4
OH
V
5.9
V
OH
OL
I
I
= –4 mA
4.5 V
6 V
3.98
5.48
OH
= –5.2 mA
OH
2 V
0.1
0.1
0.1
0.26
0.26
±0.1
8
0.1
0.1
0.1
0.4
0.4
±1
I
= 20
A
4.5 V
6 V
OL
V
V
I
I
= 4 mA
4.5 V
6 V
OL
= 5.2 mA
OL
I
I
V = V
or GND
or GND,
6 V
A
A
I
I
CC
CC
V = V
I = 0
O
6 V
160
10
CC
I
C
10
pF
IN
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2 V
CC
CD54HC160
CD54HC162
T
A
= 25°C
UNIT
MIN
6
MAX
MIN
4
MAX
f
t
Maximum frequency
Pulse duration
CLK
MHz
ns
max
CLK low
80
100
60
50
60
65
75
3
120
150
90
75
90
100
110
3
w
CLR low (’160 only)
Data (A, B, C, and D)
ENP, ENT
t
LOAD low
ns
ns
Setup time before CLK↑
Hold time after CLK↑
su
h
CLR (’162 only)
CLR high (’160 only)
Data (A, B, C, and D)
ENP, ENT
t
0
0
LOAD low
3
3
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 4.5 V
CC
CD54HC160
CD54HC162
T
A
= 25°C
UNIT
MIN
30
16
20
12
10
12
13
15
3
MAX
MIN
20
24
30
18
15
18
20
22
3
MAX
f
t
Maximum frequency
Pulse duration
CLK
MHz
ns
max
CLK low
w
CLR low (’160 only)
Data (A, B, C, and D)
ENP, ENT
t
LOAD low
ns
Setup time before CLK↑
Hold time after CLK↑
su
h
CLR (’162 only)
CLR high (’160 only)
Data (A, B, C, and D)
ENP, ENT
t
0
0
ns
LOAD low
3
3
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 6 V
UNIT
CC
CD54HC160
CD54HC162
T
A
= 25°C
MIN
35
14
17
10
9
MAX
MIN
24
20
26
15
13
15
17
19
3
MAX
f
t
Maximum frequency
Pulse duration
CLK
MHz
ns
max
CLK low
w
CLR low (’160 only)
Data (A, B, C, and D)
ENP, ENT
t
LOAD low
10
11
13
3
ns
ns
Setup time before CLK↑
Hold time after CLK↑
su
h
CLR (’162 only)
CLR high (’160 only)
Data (A, B, C, and D)
ENP, ENT
t
0
0
LOAD low
3
3
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
switching characteristics over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2 V
CC
CD54HC160
CD54HC162
T
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
UNIT
MIN
MAX
185
185
185
185
120
120
210
210
75
MIN
MAX
280
280
280
280
180
180
315
315
110
110
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
C
C
C
C
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
ns
ns
ns
ns
ns
CLK
CLK
ENT
CLR
RCO
Q
L
L
L
L
L
RCO
Q (’160 only)
t
PHL
RCO (’160 only)
t
t
TLH
75
THL
switching characteristics over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 4.5 V
CC
CD54HC160
CD54HC162
T
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
UNIT
MIN
MAX
37
37
37
37
24
24
42
42
15
15
MIN
MAX
56
56
56
56
36
36
63
63
22
22
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
C
C
C
C
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
ns
ns
ns
ns
ns
CLK
CLK
ENT
CLR
RCO
Q
L
L
L
L
L
RCO
Q (’160 only)
t
PHL
RCO (’160 only)
t
t
TLH
THL
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
switching characteristics over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 6 V
CC
CD54HC160
CD54HC162
T
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
UNIT
MIN
MAX
31
31
31
31
20
20
36
36
13
13
MIN
MAX
48
48
48
48
31
31
54
54
19
19
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
C
C
C
C
C
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
ns
ns
ns
ns
ns
CLK
CLK
ENT
CLR
RCO
Q
L
L
L
L
L
RCO
Q (’160 only)
t
PHL
RCO (’160 only)
t
t
TLH
THL
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54HC160, CD54HC162
BCD SYNCHRONOUS DECADE COUNTERS
SCHS301 – JUNE 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
S1
S2
t
t
t
t
Open
Closed
S1
S2
PZH
PZL
PHZ
PLZ
Test
Point
t
en
Closed
Open
Open
Closed
Open
R
= 1 kΩ
L
From Output
Under Test
t
t
dis
pd
C
L
Closed
Open
(see Note A)
or t
Open
t
LOAD CIRCUIT
V
CC
CLR
Input
50% V
CC
V
CC
0 V
V
Input
50% V
50% V
t
CC
PHL
90%
CC
t
0 V
rec
t
CC
PLH
50% V
CLK
CC
V
OH
In-Phase
Output
90%
t
0 V
50% V
CC
50% V
CC
V
10%
10%
t
VOLTAGE WAVEFORMS
RECOVERY TIME
OL
r
f
t
t
PHL
90%
PLH
V
V
OH
90%
V
CC
Out-of-Phase
Output
50% V
50% V
10%
CC
10%
CC
Output
Control
50% V
50% V
CC
CC
OL
0 V
t
t
r
f
t
t
PLZ
PZL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
≈V
CC
≈V
CC
50%
Output
Waveform 1
(See Note B)
10%
V
OL
t
t
V
PZH
PHZ
CC
90%
t
90%
Input
50%
10%
50% V
10%
V
OH
CC
0 V
Output
Waveform 2
(See Note B)
90%
50% V
CC
≈0 V
t
f
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
Drawing
CD54HC160F3A
CD54HC162F3A
OBSOLETE
OBSOLETE
J
J
16
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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相关型号：
CD54HC160F/3
Decade Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS, CDIP16, CERAMIC, DIP-16
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CD54HC160H/3A
Decade Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Up Direction, CMOS
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