CD54HC165 [TI]
High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register; 高速CMOS逻辑8位并行输入/串行输出移位寄存器
| 型号： | CD54HC165 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register |
| 文件： | 总13页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC165, CD74HC165,
CD54HCT165, CD74HCT165
Data sheet acquired from Harris Semiconductor
SCHS156C
High-Speed CMOS Logic
February 1998 - Revised October 2003
8-Bit Parallel-In/Serial-Out Shift Register
Features
Description
• Buffered Inputs
The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift
registers with complementary serial outputs (Q and Q )
7
7
• Asynchronous Parallel Load
• Complementary Outputs
[ /Title
(CD74H
C165,
CD74H
CT165)
/Subject
(High
available from the last stage. When the parallel load (PL)
input is LOW, parallel data from the D0 to D7 inputs are
loaded into the register asynchronously. When the PL is
HIGH, data enters the register serially at the DS input and
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
shifts one place to the right (Q →Q →Q , etc.) with each
0
1
2
positive-going clock transition. This feature allows parallel-
o
o
to-serial converter expansion by typing the Q output to the
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
7
DS input of the succeeding device.
For predictable operation the LOW-to-HIGH transition of CE
should only take place while CP is HIGH. Also, CP an d CE
should be LOW before the LOW-to-HIGH transition of PL to
prevent shifting the data when PL goes HIGH.
Speed
• Significant Power Reduction Compared to LSTTL
Logic ICs
CMOS
Logic 8-
Bit Par-
allel-
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
CC
Ordering Information
IL
IH
at V
= 5V
CC
TEMP. RANGE
o
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
PART NUMBER
CD54HC165F3A
CD54HCT165F3A
CD74HC165E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
CD74HC165M
Pinout
CD74HC165MT
CD54HC165M96
CD74HCT165E
CD74HCT165M
CD74HCT165MT
CD54HCT165M96
CD54HC165, CD54HCT165
(CERDIP)
CD74HC165, CD74HCT165
(PDIP, SOIC)
TOP VIEW
PL
CP
D4
D5
D6
D7
1
2
3
4
5
6
7
8
16 V
CC
15 CE
14 D3
13 D2
12 D1
11 D0
10 DS
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Q
7
9
Q
7
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Functional Diagram
11
12
13
14
3
D0
D1
D2
D3
D4
D5
D6
D7
DS
PARALLEL
DATA
INPUTS
4
5
9
7
Q
Q
7
7
SERIAL
OUTPUTS
6
10
1 15
2
PL
CE
CP
GND = 8
VCC = 16
TRUTH TABLE
INPUTS
Q
REGISTER
OUTPUTS
n
OPERATING MODE
Parallel Load
PL
L
CE
X
CP
X
X
↑
DS
X
X
l
D0 - D7
Q
Q
- Q
Q
Q
7
0
1
6
7
L
H
X
X
X
L
H
L
L-L
H-H
L
H
L
X
H
L
Serial Shift
H
H
H
L
q
q
q
q
q
q
q
q
0 -
0 -
1 -
5
6
6
7
6
6
7
L
↑
h
H
q
q
q
q
5
6
Hold Do Nothing
H
X
X
q
0
H =High Voltage Level
h
l
L
X
↑
= High Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition
= Low Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition
= Low Voltage Level
= Don’t Care
= Transition from Low to High Level
q
= Lower Case Letters Indicate The State Of the Reference Output Clock Transition
n
2
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
67
73
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
DC Drain Current per Output, IO
For V < -0.5V V > V + 0.5V . . . . . . . . . . . . . . . . . . . . . .±25mA
o
O
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
Input Leakage
Current
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
GND
3
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
V
or
IH
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
DS, D0 to D7
CP, PL
UNIT LOADS
0.35
0.65
NOTE: Unit Load is ∆I
CC
Specifications table, e.g. 360µA max at 25 C.
limit specified in DC Electrical
o
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
HC TYPES
CP Pulse Width
t
t
2
80
16
14
-
-
-
100
20
-
-
-
120
24
-
-
-
ns
ns
ns
WL, WH
4.5
6
17
20
4
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
PL Pulse Width
SYMBOL
V
(V)
MIN
80
16
14
80
16
14
80
16
14
80
16
14
35
7
MAX
MIN
100
20
17
100
20
17
100
20
17
100
20
17
45
9
MAX
MIN
120
24
20
120
24
20
120
24
20
120
24
20
55
11
9
MAX
UNITS
ns
CC
t
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WL
4.5
ns
6
2
ns
Set-up Time
DS to CP
t
ns
SU
4.5
6
ns
ns
CE to CP
t
2
ns
SU(L)
4.5
6
ns
ns
D0-D7 to PL
t
2
ns
SU
4.5
6
ns
ns
Hold Time
t
t
2
ns
H
H
DS to CP or CE
4.5
6
ns
6
8
ns
CE to CP
2
0
0
0
ns
4.5
6
0
0
0
ns
0
0
0
ns
Recovery Time
PL to CP
t
2
100
20
17
6
125
25
21
5
150
30
26
4
ns
REC
4.5
6
ns
ns
Maximum Clock Pulse
Frequency
f
2
MHz
MHz
MHz
MAX
4.5
6
30
35
24
28
20
24
HCT TYPES
CP Pulse Width
t
, t
WL WH
4.5
4.5
4.5
18
20
20
-
-
-
23
25
25
-
-
-
27
30
30
-
-
-
ns
ns
ns
PL Pulse Width
t
WL
Set-up Time
DS to CP
t
SU
CE to CP
t
4.5
6
20
20
7
-
-
-
25
25
9
-
-
-
30
30
11
-
-
-
ns
ns
ns
SU(L)
D0-D7 to PL
t
SU
Hold Time
t
4.5
H
DS to CP or CE
CE to CP
t , t
4.5
4.5
0
-
-
0
-
-
0
-
-
ns
ns
S
H
Recovery Time
PL to CP
t
20
25
30
REC
Maximum Clock Pulse
Frequency
f
4.5
27
-
22
-
18
-
MHz
MAX
5
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
CONDITIONS
PARAMETER
SYMBOL
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
HC TYPES
Propagation Delay
t
t
t
, t
C = 50pF
2
-
-
165
33
-
205
41
-
250
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
L
CP or CE to Q or Q
4.5
7
7
C = 15pF
5
6
2
13
-
L
C = 50pF
28
175
35
-
35
220
44
-
43
265
53
-
L
PL to Q or Q
, t
PLH PHL
C = 50pF
-
7
7
L
4.5
5
-
C = 15pF
14
-
L
C = 50pF
6
30
150
30
-
37
190
38
-
45
225
45
-
L
D7 to Q or Q
, t
PLH PHL
C = 50pF
2
-
7
7
L
4.5
5
-
C = 15pF
12
-
L
C = 50pF
6
26
75
15
13
10
-
33
95
19
16
10
-
38
110
22
19
10
-
L
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
-
4.5
6
-
-
C
-
-
-
-
IN
Power Dissipation
Capacitance
C
5
17
PD
(Notes 3, 4)
HCT TYPES
Propagation Delay
t
t
t
, t
C = 50pF
4.5
5
-
17
-
40
-
50
-
60
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
L
CP or CE to Q or Q
C = 15pF
L
7
7
PL to Q or Q
, t
PLH PHL
C = 50pF
4.5
5
40
-
50
-
60
-
7
7
L
C = 15pF
17
-
L
D7 to Q or Q
, t
PLH PHL
C = 50pF
4.5
5
35
-
44
-
53
-
7
7
L
C = 15pF
14
-
L
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
4.5
-
15
10
19
10
-
22
10
-
L
C
C = 50pF
L
-
IN
Power Dissipation
Capacitance
C
-
5
24
PD
(Notes 3, 4)
NOTES:
3. C
is used to determine the dynamic power consumption, per package.
PD
4. P = V
2
2
f + ∑ (C V
CC
+ f ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply
CC
D
CC
i
L
O
i
O
L
Voltage.
6
CD54HC165, CD74HC165, CD54HCT165, CD74HCT165
Test Circuits and Waveforms
t
t
r
f
90%
10%
CP OR CE
V
S
GND
t
W
t
W
INPUT LEVEL
1/f
PL
MAX
V
S
t
PHL
t
PLH
90%
10%
t
t
PLH
PHL
Q
OR Q
t
V
7
7
S
V
Q
OR Q
S
7
7
t
TLH
THL
FIGURE 3. SERIAL-SHIFT MODE
FIGURE 4. PARALLEL-LOAD MODE
t
t
f
r
INPUT LEVEL
GND
90%
10%
VALID
INPUT D7
t
INPUT LEVEL
GND
INPUTS D0-D7
t
V
S
t
PLH
PHL
90%
10%
t
SU
H
Q
OR Q
7
7
V
S
INPUT LEVEL
V
PL
S
t
t
TLH
THL
GND
FIGURE 5. PARALLEL-LOAD MODE
FIGURE 6. PARALLEL-LOAD MODE
VALID
INPUT LEVEL
INPUT LEVEL
INPUTS DS
CP OR CE
PL
V
S
GND
GND
t
t
H
t
SU
REC
INPUT LEVEL
INPUT LEVEL
GND
CP OR CE
V
S
GND
FIGURE 7. SERIAL-SHIFT MODE
FIGURE 8. SERIAL-SHIFT MODE
CE INHIBITED
INPUT LEVEL
GND
CP
t
t
(L)
t
t
(L)
CP
INHIBITED
SU
SU
SU
SU
INPUT LEVEL
GND
CE
FIGURE 9. SERIAL-SHIFT, CLOCK-INHIBIT MODE
7
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
PDIP
Drawing
5962-8685501EA
CD54HC165F3A
CD54HCT165F3A
CD74HC165E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
16
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
J
1
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC165EE4
CD74HC165M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
N
D
D
D
D
D
D
N
N
D
D
D
D
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC165M96
CD74HC165M96E4
CD74HC165ME4
CD74HC165MT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC165MTE4
CD74HCT165E
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HCT165EE4
CD74HCT165M
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT165M96
CD74HCT165M96E4
CD74HCT165ME4
CD74HCT165MT
CD74HCT165MTE4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
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is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
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Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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