CD54HC192F3A [TI]
High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters; 高速CMOS逻辑可预置同步4位加/减计数器
| 型号： | CD54HC192F3A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters |
| 文件： | 总16页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54/74HC192,
CD54/74HC193, CD54/74HCT193
Data sheet acquired from Harris Semiconductor
SCHS163F
High-Speed CMOS Logic
Presettable Synchronous 4-Bit Up/Down Counters
September 1997 - Revised October 2003
Presetting the counter to the number on the preset data inputs
(P0-P3) is accomplished by a LOW asynchronous parallel
Features
• Synchronous Counting and Asynchronous
Loading
load input (PL). The counter is incremented on the low-to-high
transition of the Clock-Up input (and a high level on the Clock-
Down input) and decremented on the low to high transition of
the Clock-Down input (and a high level on the Clock-up input).
A high level on the MR input overrides any other input to clear
the counter to its zero state. The Terminal Count up (carry)
goes low half a clock period before the zero count is reached
and returns to a high level at the zero count. The Terminal
Count Down (borrow) in the count down mode likewise goes
low half a clock period before the maximum count (9 in the
192 and 15 in the 193) and returns to high at the maximum
count. Cascading is effected by connecting the carry and
borrow outputs of a less significant counter to the Clock-Up
and Clock-Down inputs, respectively, of the next most
significant counter.
[ /Title
(CD74
HC192
,
CD74
HC193
,
CD74
HCT19
3)
• Two Outputs for N-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
/Sub-
ject
• HC Types
- 2V to 6V Operation
If a decade counter is preset to an illegal state or assumes an
illegal state when power is applied, it will return to the normal
sequence in one count as shown in state diagram.
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
(High
Speed
CMOS
Logic
Preset-
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
Ordering Information
TEMP. RANGE
o
V = 0.8V (Max), V = 2V (Min)
IL IH
PART NUMBER
CD54HC192F3A
CD54HC193F3A
CD54HCT193F3A
CD74HC192E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Description
The ’HC192, ’HC193 and ’HCT193 are asynchronously
presettable BCD Decade and Binary Up/Down synchronous
counters, respectively.
CD74HC192NSR
CD74HC192PW
CD74HC192PWR
CD74HC192PWT
CD74HC193E
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
Pinout
CD54HC192, CD54HC193, CD54HCT193 (CERDIP)
CD74HC192 (PDIP, SOP, TSSOP)
CD74HC193 (PDIP, SOIC)
CD74HCT193 (PDIP)
TOP VIEW
CD74HC193M
16 Ld SOIC
P1
Q1
1
2
3
4
5
6
7
8
16 V
CC
CD74HC193MT
CD74HC193M96
CD74HCT193E
16 Ld SOIC
15 P0
16 Ld SOIC
Q0
14 MR
13 TCD
12 TCU
11 PL
10 P2
CPD
CPU
Q2
16 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Q3
9
P3
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54/74HC192, CD54/74HC193, CD54/74HCT193
Functional Diagram
BCD/BINARY
PRESET
P0 P1 P2 P3
15
1
10
9
ASYN.
PARALLEL
LOAD
3
11
14
5
Q
Q
Q
0
1
2
PL
2
ENABLE
BCD (192)
BINARY (193)
OUTPUTS
MASTER
RESET
6
7
Q
3
CLOCK UP
12
13
TERMINAL
COUNT UP
4
CLOCK DOWN
TERMINAL
COUNT DOWN
TRUTH TABLE
CLOCK
DOWN
PARALLEL
LOAD
CLOCK UP
RESET
FUNCTION
Count Up
↑
H
↑
L
L
H
H
X
L
H
X
X
Count Down
Reset
X
X
H
L
Load Preset Inputs
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to
High Level
2
CD54/74HC192, CD54/74HC193, CD54/74HCT193
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Package Thermal Impedance, θ (see Note 1):
JA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
CC
DC Input Diode Current, I
For V < -0.5V or V > V
o
IK
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
o
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
o
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
V
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
8
80
160
CC
CC
GND
3
CD54/74HC192, CD54/74HC193, CD54/74HCT193
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HCT TYPES
SYMBOL V (V)
I
(mA)
V (V) MIN TYP MAX
CC
MIN
MAX
MIN
MAX
UNITS
I
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
-
-
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
- 2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
P0-P3
0.4
MR
PL
1.45
0.85
1.45
CPU, CPD
NOTE: Unit Load is ∆I
Specifications table, e.g. 360µA max at 25 C.
limit specified in DC Electrical
o
CC
4
CD54/74HC192, CD54/74HC193, CD54/74HCT193
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
Pulse Width
CPU, CPD
t
t
t
t
2
4.5
6
115
23
20
100
20
17
80
16
14
100
20
17
80
16
14
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
145
29
25
125
25
21
100
20
17
125
25
21
100
20
17
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
175
35
30
150
30
26
120
24
20
150
30
26
120
24
20
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
W
W
W
W
192
193
ns
2
ns
CPU, CPD
PL
4.5
6
ns
ns
2
ns
4.5
6
ns
ns
MR
2
ns
4.5
6
ns
ns
Set-up Time
Pn to PL
t
2
ns
SU
4.5
6
ns
ns
Hold Time
Pn to PL
t
t
2
ns
H
H
4.5
6
0
0
0
ns
0
0
0
ns
Hold Time
2
80
16
14
80
16
14
5
100
20
17
100
20
17
5
120
24
20
120
24
20
5
ns
CPD to CPU or
CPU to CPD
4.5
6
ns
ns
Recovery Time
PL to CPU, CPD
t
t
2
ns
REC
REC
MAX
MAX
4.5
6
ns
ns
MR to CPU, CPD
2
ns
4.5
6
5
5
5
ns
5
5
5
ns
Maximum Frequency
CPU, CPD
f
f
2
5
4
3
MHz
MHz
MHz
MHz
MHz
MHz
4.5
6
22
24
5
18
21
4
15
18
3
192
193
2
CPU, CPD
4.5
6
25
29
20
24
17
20
HCT TYPES
Pulse Width
t
t
2
4.5
6
-
23
-
-
-
-
-
-
-
-
-
-
-
-
-
-
29
-
-
-
-
-
-
-
-
35
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
W
CPU, CPD
CPU, CPD
192
193
2
-
-
-
W
4.5
6
23
-
29
-
35
-
5
CD54/74HC192, CD54/74HC193, CD54/74HCT193
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
V
CC
PARAMETER
SYMBOL
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
ns
PL
t
2
-
16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W
W
4.5
6
ns
ns
MR
t
2
-
-
-
ns
4.5
6
20
-
25
-
30
-
ns
ns
Set-up Time
Pn to PL
t
2
-
-
-
ns
SU
4.5
6
15
-
19
-
22
-
ns
ns
Hold Time
Pn to PL
t
t
2
-
-
-
ns
H
H
4.5
6
0
-
0
-
0
-
ns
ns
Hold Time
2
-
-
-
ns
CPD to CPU or
4.5
6
16
-
20
-
24
-
ns
CPU to CPD
Recovery Time
PL to CPU, CPD
ns
t
t
2
-
-
-
ns
REC
REC
MAX
MAX
4.5
6
15
-
19
-
22
-
ns
ns
MR to CPU, CPD
2
-
-
-
ns
4.5
6
5
-
5
-
5
-
ns
ns
Maximum Frequency
CPU, CPD
f
f
2
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
4.5
6
22
-
18
-
15
-
192
193
CPU, CPD
2
-
-
-
4.5
6
22
-
18
-
15
-
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Propagation Delay
CPU to TCU
t
, t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
125
25
-
-
-
-
-
-
-
-
-
-
-
-
-
155
31
-
-
-
-
-
-
-
-
-
-
-
-
-
190
38
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH PHL
L
C = 50pF
L
C = 15pF
10
L
C = 50pF
6
21
125
25
-
26
155
31
-
32
190
38
-
L
CPD to TCD
t
, t
PLH PHL
C = 50pF
2
-
-
L
C = 50pF
4.5
5
L
C = 15pF
10
-
L
C = 50pF
6
21
220
43
-
26
270
54
-
32
325
65
-
L
CPU to Q
t
, t
PLH PHL
C = 50pF
2
-
n
L
C = 50pF
4.5
5
-
L
C = 15pF
18
-
L
C = 50pF
6
37
46
55
L
6
CD54/74HC192, CD54/74HC193, CD54/74HCT193
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
CPD to Q
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
270
54
-
MIN
MAX
325
65
UNITS
ns
t , t
PLH PHL
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
220
43
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
n
L
C = 50pF
ns
L
C = 15pF
18
-
ns
L
C = 50pF
6
37
220
44
-
46
275
55
-
55
330
66
-
ns
L
PL to Q
t , t
PLH PHL
C = 50pF
2
-
ns
n
L
C = 50pF
4.5
5
-
ns
L
C = 15pF
18
-
ns
L
C = 50pF
6
37
200
40
-
47
250
50
-
56
300
60
-
ns
L
MR to Q
t
C = 50pF
2
-
ns
n
PHL
L
C = 50pF
4.5
5
-
ns
L
C = 15pF
17
-
ns
L
C = 50pF
6
34
75
15
13
10
-
43
95
19
16
10
-
51
110
22
19
10
-
ns
L
Transition Time
Q, TCU, TCD
t
, t
C = 50pF
2
-
ns
TLH THL
L
4.5
6
-
ns
-
ns
Input Capacitance
C
C = 50pF
-
-
pF
pF
IN
L
Power Dissipation Capacitance
(Notes 3, 4)
C
C = 15pF
5
40
PD
L
HCT TYPES
Propagation Delay
t
, t
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
11
-
27
-
-
-
-
-
-
-
-
-
-
-
-
-
34
-
-
-
-
-
-
-
-
-
-
-
-
-
41
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH PHL
L
CPU to TCU
CPU to TCD
C = 15pF
L
t
t
t
t
, t
C = 50pF
4.5
5
27
-
34
-
41
-
PLH PHL
L
C = 15pF
11
-
L
CPU to Q
CPD to Q
, t
PLH PHL
C = 50pF
4.5
5
40
-
50
-
60
-
n
L
C = 15pF
17
-
L
, t
PLH PHL
C = 50pF
4.5
5
40
-
50
-
60
-
n
L
C = 15pF
17
-
L
PL to Q
, t
PLH PHL
C = 50pF
4.5
5
46
-
58
-
69
-
n
L
C = 15pF
21
-
L
MR to Q
t
C = 50pF
4.5
5
43
-
54
-
65
-
n
PHL
L
C = 15pF
18
L
Transition Time
Q, TCU, TCD
t
, t
C = 50pF
L
TLH THL
4.5
-
-
-
-
-
-
15
10
-
-
-
-
19
10
-
-
-
-
22
10
-
ns
pF
pF
Input Capacitance
C
C = 50pF
L
IN
Power Dissipation Capacitance
(Notes 3, 4)
C
C = 15pF
5
50
PD
L
NOTES:
3. C
is used to determine the dynamic power consumption, per gate.
PD
4. P = V
2
2
f + ∑ (C V
) where f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage.
CC
D
CC
i
L
CC
i
L
7
CD54/74HC192, CD54/74HC193, CD54/74HCT193
Test Circuits and Waveforms
MASTER RESET
ASYNCHRONOUS PARALLEL LOAD
P0
P1
PRESET DATA
P2
P3
SEQUENCES:
1. RESET OUTPUTS TO ZERO.
CLOCK UP
2. LOAD (PRESET) TO BCD SEVEN.
3. COUNT UP TO EIGHT, NINE,
TERMINAL COUNT UP, ZERO,
ONE AND TWO.
4. COUNT DOWN TO ONE, ZERO,
TERMINAL COUNT DOWN, NINE,
EIGHT AND SEVEN.
CLOCK DOWN
Q
0
1
2
Q
Q
OUTPUTS
Q
3
TERMINAL COUNT UP
TERMINAL COUNT DOWN
8
9
0
1
2
1
0
9
8
7
0
7
RESET PRESET
COUNT UP
COUNT DOWN
FIGURE 1. ’HC192 SYNCHRONOUS DECADE COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES
8
CD54/74HC192, CD54/74HC193, CD54/74HCT193
Test Circuits and Waveforms (Continued)
MASTER RESET
ASYNCHRONOUS PARALLEL LOAD
P0
P1
PRESET DATA
P2
P3
SEQUENCES:
1. RESET OUTPUTS TO ZERO.
2. LOAD (PRESET) TO BINARY THIRTEEN.
3. COUNT UP TO FOURTEEN,
FIFTEEN, TERMINAL COUNT UP,
ZERO, ONE AND TWO.
CLOCK UP
CLOCK DOWN
4. COUNT DOWN TO ONE, ZERO,
TERMINAL COUNT DOWN,
FIFTEEN, FOURTEEN AND
Q
0
1
2
Q
Q
THIRTEEN.
OUTPUTS
Q
3
TERMINAL COUNT UP
TERMINAL COUNT DOWN
14 15
0
1
2
1
0
15 14 13
0
13
NOTES:
RESET PRESET
COUNT UP
COUNT DOWN
1. Master reset overrides load data and clock inputs.
2. When counting up, clock-down input must be high.
When counting down, clock-up input must be high.
FIGURE 2. ’HC193 SYNCHRONOUS BINARY COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES
l/f
MAX
INPUT LEVEL
CPU OR CPD
INPUT LEVEL
V
V
V
S
S
S
V
V
S
CPU OR CPD
TCU OR TCD
S
t
W
t
t
PLH
PHL
t
t
PHL
PLH
V
V
S
S
V
Q
n
S
V
S
FIGURE 3. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE
WIDTH
FIGURE 4. CLOCK TO TERMINAL COUNT DELAYS
INPUT LEVEL
Pn
INPUT LEVEL
t
t
W
MR
V
V
S
W
S
t
INPUT LEVEL
V
V
S
S
V
V
PL
t
REC
S
S
W
t
CPU OR CPD
REC
INPUT LEVEL
V
S
CPU OR CPD
V
S
t
PHL
t
t
PHL
PLH
INPUT LEVEL
Q
n
V
S
Q
n
V
V
S
S
FIGURE 5. PARALLEL LOAD PULSE WIDTH, PARALLEL
LOAD TO OUTPUT DELAYS, AND PARALLEL
LOAD TO CLOCK RECOVERY TIME
FIGURE 6. MASTER RESET PULSE WIDTH, MASTER RESET
TO OUTPUT DELAY AND MASTER RESET TO
CLOCK RECOVERY TIME
9
Test Circuits and Waveforms (Continued)
V
INPUT LEVEL
INPUT LEVEL
S
Pn
t
(H)
t
(L)
SU
SU
t
t
H
H
V
V
PL
S
S
Q = p
Q = p
Q
n
FIGURE 7. SET-UP AND HOLD TIMES DATA TO PARALLEL LOAD (PL)
DATA INPUT
P0 P1 P2 P3
P0 P1 P2 P3
UP CLOCK
BORROW
CARRY
CPU
CPD
PL
TCU
TCD
MR
CPU
CPD
PL
TCU
TCD
MR
DOWN CLOCK
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
0
1
2 3
ASYNCHRONOUS,
PARALLEL LOAD
RESET
OUTPUT
FIGURE 8. CASCADED UP/DOWN COUNTER WITH PARALLEL LOAD
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
15
14
13
15
14
13
12
11
10
9
12
11
10
9
COUNT DOWN
COUNT UP
NOTE: Illegal states in BCD counters corrected in one count.
NOTE: Illegal states in BCD counters corrected in one or two counts.
FIGURE 9. ’HC192, ’HCT193 STATE DIAGRAMS
10
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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