CD54HC259F3A [TI]
High-Speed CMOS Logic 8-Bit Addressable Latch; 高速CMOS逻辑8位可寻址锁存器
| 型号： | CD54HC259F3A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic 8-Bit Addressable Latch |
| 文件： | 总12页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC259, CD74HC259,
CD54HCT259, CD74HCT259
Data sheet acquired from Harris Semiconductor
SCHS173C
High-Speed CMOS Logic
8-Bit Addressable Latch
November 1997 - Revised October 2003
Features
Description
• Buffered Inputs and Outputs
• Four Operating Modes
• Typical Propagation Delay of 15ns at V
The ’HC259 and ’HCT259 Addressable Latch features the
low-power consumption associated with CMOS circuitry and
has speeds comparable to low-power Schottky.
[ /Title
(CD74
HC259
,
CD74
HCT25
9)
= 5V,
CC
This latches three active modes and one reset mode. When
both the Latch Enable (LE) and Master Reset (MR) inputs are
low (8-line Demultiplexer mode) the output of the addressed
latch follows the Data input and all other outputs are forced
low. When both MR and LE are high (Memory Mode), all
outputs are isolated from the Data input, i.e., all latches hold
o
C = 15pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C the last data presented before the LE transition from low to
high. A condition of LE low and MR high (Addressable Latch
mode) allows the addressed latch’s output to follow the data
input; all other latches are unaffected. The Reset mode (all
outputs low) results when LE is high and MR is low.
/Sub-
ject
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
(High
Speed
CMOS
Logic
8-Bit
Addres
sable
Latch)
• HC Types
Ordering Information
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
CC
TEMP. RANGE
o
IL
IH
PART NUMBER
CD54HC259F3A
CD54HCT259F3A
CD74HC259E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
at V
= 5V
CC
• HCT Types
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
CD74HC259M
CD74HC259MT
CD74HC259M96
CD74HCT259E
CD74HCT259M
CD74HCT259MT
CD74HCT259M96
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Pinout
CD54HC259, CD54HCT259
(CERDIP)
CD74HC259, CD74HCT259
(PDIP, SOIC)
TOP VIEW
A0
A1
1
2
3
4
5
6
7
8
16 V
CC
15 MR
14 LE
13 D
A2
Q0
Q1
12 Q7
11 Q6
10 Q5
Q2
Q3
9
Q4
GND
Functional Diagram
4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
5
A
A
A
0
1
2
8
6
1-OF-8
DECODER
LATCHES
7
3
9
10
11
12
14
LE
15
13
MR
D
GND = 8
= 16
V
CC
TRUTH TABLE
OUTPUT OF
LATCH SELECTION TABLE
SELECT INPUTS
INPUTS
LATCH
ADDRESS
LATCH
EACH OTHER
OUTPUT
A2
L
A1
L
A0
L
ADDRESSED
MR
LE
FUNCTION
0
1
2
3
4
5
6
7
H
L
D
Q
Addressable
Latch
io
L
L
H
L
L
H
H
L
H
L
H
L
Q
Q
Memory
io
io
L
H
L
D
L
8-Line
Demultiplexer
H
H
H
H
L
H
L
L
H
L
L
Reset
H
H
H = High Voltage Level
L = Low Voltage Level
H
D = The level at the data input
Q
= The level of Q (i = 0, 1...7, as appropriate) before the indicat-
i
io
ed steady-state input conditions were established.
2
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
CC
DC Input Diode Current, I
For V < -0.5V or V > V
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
A0 - A2, LE
D
UNIT LOADS
1.5
1.2
MR
0.75
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V) MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
Pulse Width
LE
t
WL
2
70
-
-
-
-
-
-
90
18
15
-
-
-
-
-
-
105
21
-
-
-
-
-
-
ns
ns
ns
4.5
6
14
12
18
4
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
MR
SYMBOL
V
(V) MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
t
2
70
-
-
-
-
-
-
90
18
15
-
-
-
-
-
-
105
21
-
-
-
-
-
-
ns
ns
ns
WL
4.5
6
14
12
18
Setup Time
t
SU
D to LE
A to LE
2
4.5
6
80
16
14
-
-
-
-
-
-
100
20
-
-
-
-
-
-
120
24
-
-
-
-
-
-
ns
ns
ns
17
20
Hold Time
t
H
D to LE
A to LE
2
4.5
6
0
0
0
-
-
-
-
-
-
0
0
0
-
-
-
-
-
-
0
0
0
-
-
-
-
-
-
ns
ns
ns
HCT TYPES
Pulse Width
LE
MR
t
4.5
4.5
4.5
18
17
0
-
-
-
-
-
-
23
21
0
-
-
-
-
-
-
27
26
0
-
-
-
-
-
-
ns
ns
ns
WL
Setup Time
D to LE
A to LE
t
SU
Hold Time
D to LE
t
H
A to LE
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
D to Q
t
PHL
C
= 50pF
L
2
-
-
-
185
37
-
-
-
-
-
-
-
-
-
230
46
-
-
-
-
-
-
-
-
-
280
56
-
ns
ns
ns
ns
ns
ns
ns
ns
4.5
5
-
-
-
-
-
-
-
C
C
C
= 15pF
= 50pF
= 50pF
15
-
L
L
L
6
31
170
34
-
39
215
43
-
48
255
51
-
LE to Q
t
2
-
PHL
4.5
5
-
C
C
= 15pF
= 50pF
14
-
L
6
29
37
43
L
5
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
A to Q
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
t
C
= 50pF
2
-
-
-
185
37
-
-
-
-
-
-
-
-
-
-
-
-
-
230
46
-
-
-
-
-
-
-
-
-
-
-
-
-
280
56
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
PHL
L
4.5
5
-
-
-
-
-
-
-
-
-
-
-
C
C
C
= 15pF
= 50pF
= 50pF
15
-
L
L
L
6
31
155
31
-
39
195
39
-
48
235
47
-
MR to Q
t
t
2
-
PHL, PLH
4.5
5
-
C
C
C
= 15pF
= 50pF
= 50pF
13
-
L
L
L
6
26
75
15
13
-
33
95
19
16
-
40
110
22
19
-
Output Transition Time
t
, t
THL TLH
2
-
4.5
6
-
-
Power Dissipation Capacitance
(Notes 3, 4)
C
C
C
= 15pF
= 50pF
5
21
PD
L
Input Capacitance
C
-
10
-
10
-
10
-
10
pF
I
L
HCT TYPES
Propagation Delay
D to Q
t
t
PHL, PLH
C
C
C
C
C
C
C
C
C
= 50pF
= 15pF
= 50pF
= 15pF
= 50pF
= 15pF
= 50pF
= 15pF
= 15pF
4.5
5
-
-
-
-
-
-
-
-
-
-
39
-
-
-
-
-
-
-
-
-
-
49
-
-
-
-
-
-
-
-
-
-
59
-
ns
ns
ns
ns
ns
ns
ns
ns
pF
L
L
L
L
L
L
L
L
L
16
-
LE to Q
A to Q
4.5
5
38
-
48
-
57
-
16
-
4.5
5
41
-
51
-
61
-
17
-
MR to Q
4.5
5
39
-
49
-
59
-
16
22
Power Dissipation Capacitance
(Notes 3, 4)
C
5
-
-
-
PD
Input Capacitance
Output Transition Time
NOTES:
C
C
C
= 50pF
= 50pF
-
10
-
-
-
10
15
-
-
10
19
-
-
10
22
pF
ns
I
L
t
, t
THL TLH
4.5
L
3. C
is used to determine the dynamic power consumption, per package.
PD
2
2
4. P = C
V
f + ∑ C V
f where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance,
CC O i O L
D
PD CC
i
L
V
= Supply Voltage.
CC
6
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259
Test Circuits and Waveforms (Continued)
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
8
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相关型号：
CD54HC273F/3A
IC HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20, FF/Latch
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