CD54HC354F3A [TI]
8-Line to 1-Line Data Selector/Multiplexer/Register With 3-State Outputs; 8号线到1线数据选择器/多路复用器/寄存器，三态输出
| 型号： | CD54HC354F3A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Line to 1-Line Data Selector/Multiplexer/Register With 3-State Outputs |
| 文件： | 总14页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC354, CD74HC354,
CD74HCT354
8-Line to 1-Line Data Selector/Multiplexer/Register
With 3-State Outputs
SCHS277D - November 1997 - Revised May 2003
Features
Description
• HC/HCT354
The CD54HC354, CD74HC354, and CD74HCT354 are data
selectors/multiplexers that select one of eight sources. In both
types, the data select bits S0, S1 and S2 are stored in
transparent latches that are enabled by a low latch enable
input, LE.
- Transparent Data and Select Latches
• Buffered Inputs
[ /Title
(CD74
HC354
,
• Three-State Complementary Outputs
• Bus Line Driving Capability
In the HC/HCT354 the data enable input, E, controls
transparent latches that pass data to the outputs when E is
high and latches in new data when E is low.
• Typical Propagation Delay: V
CC
= 5V, C = 15pF,
L
o
CD74
HCT35
4)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Input
Multip
lexer/
Regis-
T = 25 C
A
- Data to Output = 18ns
In both types the three-state outputs are controlled by three
output-enable inputs OE1, OE2, and OE3.
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
TEMP. RANGE
• Balanced Propagation Delay and Transition Times
o
PART NUMBER
CD54HC354F3A
CD74HC354E
( C)
PACKAGE
20 Ld CERDIP
20 Ld PDIP
• Significant Power Reduction Compared to LSTTL
Logic ICs
-55 TO 125
-55 to 125
-55 to 125
• HC Types
- 2V to 6V Operation
CD74HCT354E
20 Ld PDIP
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Pinout
CD54HC354
(CERDIP)
CD74HC354, CD74HCT354
(PDIP)
TOP VIEW
1
2
3
4
5
6
7
8
9
V
Y
D7
D6
D5
D4
D3
D2
D1
D0
E
20
19
CC
18 Y
17 OE3
16 OE2
15
OE1
14 S0
13 S1
12
S2
GND 10
11 LE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC354, CD74HC354, CD74HCT354
Functional Diagram
S0
14
S1
13
S2
12
8
D0
7
6
5
4
3
2
1
19
Y
D1
D2
D3
D4
D5
D6
D7
18
Y
11
LE
OE1
OE2
OE3
15
16
17
9
E
TRUTH TABLE
INPUTS
ENABLE
DATA
SELECT (NOTE 1 )
S1
OUTPUT ENABLES
OUTPUTS
S2
X
X
X
L
S0
X
X
X
L
E
X
X
X
L
OE1
H
X
X
L
OE2
X
H
X
L
OE3
X
Y
Z
Y
Z
X
X
X
L
X
Z
Z
L
Z
Z
H
H
H
H
H
H
H
H
H
H
H
H
H
H
D0
D0
L
L
L
H
L
L
L
D0
D0
n
n
L
L
H
H
L
L
L
D1
D1
D1
D1
L
L
H
L
L
L
n
n
L
H
H
H
H
L
L
L
D2
D2
D2
D2
L
L
H
L
L
L
n
n
L
H
H
L
L
L
D3
D3
D3
D3
L
H
L
L
L
n
n
H
H
H
H
H
H
L
L
D4
D4
D4
D4
L
L
H
L
L
L
n
n
L
H
H
L
L
L
D5
D5
D5
D5
L
H
L
L
L
n
n
H
H
L
L
D6
D6
D6
D6
L
H
L
L
n
n
2
CD54HC354, CD74HC354, CD74HCT354
TRUTH TABLE (Continued)
INPUTS
ENABLE
SELECT (NOTE 1 )
DATA
OUTPUT ENABLES
OUTPUTS
S2
H
S1
H
S0
H
E
L
OE1
OE2
OE3
H
Y
Y
L
L
L
L
D7
D7
H
H
H
H
H
D7
D7
n
n
H = High Voltage Level (Steady State); L = Low Voltage Level (Steady State); X = Don’t Care; Z = High Impedance State (Off
State); D0 ...D7 = the level of steady-state inputs D0 through D7, respectively, before the most recent low-to-high transition of
n
n
data control.
NOTE:
1. This column shows the input address setup with LE low.
Block Diagram
15
16
17
OE1
OE2
OE3
ENABLE LOGIC
9
E
8
7
6
D0
D1
D2
D3
D4
D5
D6
D
A
T
1
O
F
A
5
4
18
19
8
R
E
G
I
S
T
E
R
Y
Y
S
E
L
E
C
T
O
R
3
2
1
BUFFERS
S
D7
11
14
LE
S0
A
D
D
R
E
S
S
R
E
G
I
S
T
E
R
ADDRESS
DECODE
13
12
S1
S2
3
CD54HC354, CD74HC354, CD74HCT354
Logic Diagram
15
OE1
16
OE2
V
CC
P
17
OE3
18
Y
1 OF 8 LATCHES
E
N
P
N
E
8 (7, 6, 5, 4, 3, 2, 1)
D0
GND
E
P
N
P
N
E
E
E
V
CC
P
19
Y
N
9
TO 7 OTHER
OTHER 7
E
LATCHES
SEL0
LATCH OUTPUTS
GND
CONNECT HERE
TO OTHER 7 LATCHES
SEL0
SEL1
SEL2
SEL3
SEL4
SEL5
SEL6
SEL7
20
V
CC
10
GND
LE
P
N
LE
14
LE
SL0
SL0
P
N
S0
LE
LE
LE
P
N
13
LE
SL1
SL1
P
N
S1
LE
LE
LE
P
N
12
11
LE
SL2
SL2
P
N
S2
LE
LE
LE
LE
FIGURE 1. HC/HCT354 LOGIC DIAGRAM
4
CD54HC354, CD74HC354, CD74HCT354
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 2)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
69
o
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
DC Drain Current, per Output, I
O
(SOIC - Lead Tips Only)
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-6
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-7.8
(Bus Driver)
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
7.8
(Bus Driver)
Input Leakage
Current
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
GND
5
CD54HC354, CD74HC354, CD74HCT354
DC Electrical Specifications
(Continued)
TEST
o
o
o
o
o
CONDITIONS
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
Three-State Leakage
Current
I
V
V
or
V
=
or
6
-
-
±0.5
-
±5.0
-
±10
µA
OZ
IL
O
V
IH
CC
GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-4
0.02
4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
-
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 3)
V
4.5 to
5.5
100
360
450
CC
-2.1
Three-State Leakage
Current
I
V
V
or
V =
O
5.5
-
-
±0.5
-
±5.0
-
±10
µA
OZ
IL
V
or
IH
CC
GND
NOTE:
3. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
0.50
D0-D7
S0, S1, S3
0.70
OE1, OE2
0.80
OE3
0.25
LE
E
0.25
0.60
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
CC
6
CD54HC354, CD74HC354, CD74HCT354
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
E Pulse Width
t
, t
PLH PHL
-
-
-
-
-
-
2
80
16
14
80
16
14
50
10
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
20
17
100
20
17
65
13
11
65
13
11
55
11
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120
24
20
120
24
20
75
15
13
75
15
13
70
14
12
70
14
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5
6
LE Pulse Width
t , t
PLH PHL
2
4.5
6
Set-up Times Dn → E
Set-up Times Sn → LE
Hold Times Dn → E
Hold Times Sn → LE
t
2
SU
SU
4.5
6
t
2
50
10
9
4.5
6
t
t
2
45
9
H
H
4.5
6
8
2
45
9
55
11
9
4.5
6
8
HCT TYPES
E Pulse Width
t
, t
PLH PHL
-
-
-
-
-
-
4.5
4.5
4.5
4.5
4.5
4.5
16
16
10
10
9
-
-
-
-
-
-
-
-
-
-
-
-
20
20
13
13
11
11
-
-
-
-
-
-
24
24
15
15
14
14
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
LE Pulse Width
t , t
PLH PHL
Set-up Times Dn → E
Set-up Times Sn → LE
Hold Times Dn → E
Hold Times Sn → LE
t
SU
SU
t
t
H
H
t
9
Switching Specifications Input t , t = 6ns
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay,
Dn → Y, Y
t
, t
PLH PHL
C = 50pF
2
4.5
6
-
-
210
42
36
-
265
53
45
-
315
63
54
-
ns
ns
ns
ns
ns
ns
ns
ns
L
-
C = 15pF
5
18
-
L
Propagation Delay,
E → Y, Y
t , t
PLH PHL
C = 50pF
2
250
50
43
-
315
63
54
-
375
75
64
-
L
4.5
6
-
-
C = 15pF
5
21
L
7
CD54HC354, CD74HC354, CD74HCT354
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
260
52
44
-
MAX
325
65
55
-
MAX
390
78
66
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
CC
Propagation Delay,
Sn → Y, Y
t , t
PLH PHL
C = 50pF
2
-
-
L
4.5
6
5
2
-
C = 15pF
22
-
L
Propagation Delay,
LE → Y, Y
t , t
PLH PHL
C = 50pF
290
58
49
-
365
73
62
-
435
87
74
-
L
4.5
6
-
-
C = 15pF
5
24
-
L
Output Disabling Time,
OEn to Y, Y
t
t
t
t
, t
C = 50pF
2
155
31
26
-
195
39
33
-
235
47
40
-
PLZ PHZ
L
4.5
6
-
-
C = 15pF
5
13
-
L
Output Disabling Time,
OE3 to Y, Y
, t
PLZ PHZ
C = 50pF
2
155
31
26
-
195
39
33
-
235
47
40
-
L
4.5
6
-
-
C = 15pF
5
13
-
L
Output Enabling Time,
OEn to Y, Y
, t
PZL PZH
C = 50pF
2
150
30
26
-
190
38
33
-
225
45
38
-
L
4.5
6
-
-
C = 15pF
5
12, 13
L
Output Enabling Time,
OE3 to Y, Y
, t
PZL PZH
C = 50pF
2
-
160
32
27
-
200
40
34
-
240
48
41
-
L
4.5
6
-
-
C = 15pF
5
12, 13
L
Output Transition Time
t
, t
TLH THL
C = 50pF
L
2
-
-
60
12
10
10
20
-
75
15
13
10
20
-
90
18
15
10
20
-
4.5
6
-
Input Capacitance
C
-
-
-
-
-
I
Three-State Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
5
90
PD
(Notes 4, 5)
HCT TYPES
Propagation Delay,
Dn → Y, Y
t
, t
PLH PHL
C = 50pF
4.5
5
-
47
-
59
-
71
-
ns
ns
ns
ns
L
C = 15pF
20
-
L
Propagation Delay,
E → Y, Y
t , t
PLH PHL
C = 50pF
4.5
5
54
-
68
-
81
-
L
C = 15pF
23
L
8
CD54HC354, CD74HC354, CD74HCT354
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
59
-
MAX
74
-
MAX
89
-
UNITS
ns
CC
Propagation Delay,
Sn → Y, Y
t , t
PLH PHL
C = 50pF
4.5
-
25
-
L
C = 15pF
5
ns
L
Propagation Delay,
LE → Y, Y
t , t
PLH PHL
C = 50pF
4.5
5
63
-
79
-
94
-
ns
L
C = 15pF
25
-
ns
L
Output Disabling Time,
OEn to Y, Y
t
t
t
t
, t
C = 50pF
4.5
5
33
-
41
-
50
-
ns
PLZ PHZ
L
C = 15pF
13, 16
ns
L
Output Disabling Time,
OE3 to Y, Y
, t
PLZ PHZ
C = 50pF
4.5
5
-
39
-
49
-
59
-
ns
L
C = 15pF
13, 16
ns
L
Output Enabling Time,
OEn to Y, Y
, t
PZL PZH
C = 50pF
4.5
5
-
14
-
34
-
43
-
51
-
ns
L
C = 15pF
ns
L
Output Enabling Time,
OE3 to Y, Y
, t
PZL PZH
C = 50pF
4.5
5
34
-
43
-
51
-
ns
L
C = 15pF
14
-
ns
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
12
10
20
-
15
10
20
-
18
10
20
-
ns
C
-
-
-
-
pF
pF
pF
IN
Three-State Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
5
92
PD
(Notes 4, 5)
NOTES:
4. C
is used to determine the dynamic power consumption, per device.
2
PD
5. P = V
(C
+ C ) where f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage.
D
CC
PD
L
i
L
CC
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
0.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
9
CD54HC354, CD74HC354, CD74HCT354
Test Circuits and Waveforms (Continued)
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 4. HC AND HCT TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
10
CD54HC354, CD74HC354, CD74HCT354
Test Circuits and Waveforms (Continued)
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 8. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 9. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 10. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
11
MECHANICAL
MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
0.775
0.920
1.060
A MAX
A
(19,69) (19,69) (23,37) (26,92)
16
9
0.745
0.745
0.850
0.940
A MIN
(18,92) (18,92) (21,59) (23,88)
MS-100
VARIATION
0.260 (6,60)
0.240 (6,10)
AA
BB
AC
AD
C
1
8
0.070 (1,78)
0.045 (1,14)
D
0.045 (1,14)
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
D
0.030 (0,76)
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
14/18 PIN ONLY
20 pin vendor option
D
4040049/E 12/2002
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A).
D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
1
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相关型号：
CD54HC356F3A
HC/UH SERIES, 8 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, CDIP20, CERAMIC, DIP-20
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