首页 |元器件品牌

CD54HC73_V01 [TI]

Dual J-K Flip-Flop with Reset Negative-Edge Trigger;
CD54HC73_V01
型号： CD54HC73_V01
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Dual J-K Flip-Flop with Reset Negative-Edge Trigger
文件： 总18页 (文件大小：1007K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
CD54HC73, CD74HC73,  
CD74HCT73  
Data sheet acquired from Harris Semiconductor  
SCHS134E  
Dual J-K Flip-Flop with Reset  
Negative-Edge Trigger  
February 1998 - Revised September 2003  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise  
Immunity and Increased Input Rise and Fall Times  
The ’HC73 and CD74HCT73 utilize silicon gate CMOS  
technology to achieve operating speeds equivalent to LSTTL  
parts. They exhibit the low power consumption of standard  
CMOS integrated circuits, together with the ability to drive 10  
LSTTL loads.  
[ /Title  
(CD74  
HC73,  
CD74  
HCT73  
)
• Asynchronous Reset  
• Complementary Outputs  
• Buffered Inputs  
These flip-flops have independent J, K, Reset and Clock  
inputs and Q and Q outputs. They change state on the  
negative-going transition of the clock pulse. Reset is  
accomplished asynchronously by a low level input. This  
device is functionally identical to the HC/HCT107 but differs  
in terminal assignment and in some parametric limits.  
• Typical f  
MAX  
= 60MHz at V = 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
/Sub-  
ject  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
(Dual  
J-K  
Flip-  
Flop  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible  
with the standard LS logic family.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
PART NUMBER  
CD54HC73F3A  
CD74HC73E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC73M  
at V  
= 5V  
CC  
CD74HC73MT  
CD74HC73M96  
CD74HCT73E  
CD74HCT73M  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC73 (CERDIP)  
CD74HC73, CD74HCT73 (PDIP, SOIC)  
TOP VIEW  
1CP  
1R  
1
2
3
4
5
6
7
14 1J  
13 1Q  
12 1Q  
11 GND  
10 2K  
1K  
V
CC  
2CP  
2R  
9
8
2Q  
2Q  
2J  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD54HC73, CD74HC73, CD74HCT73  
Functional Diagram  
14  
12  
1J  
1Q  
3
FF 1  
13  
1K  
1Q  
1
2
1CP  
1R  
7
10  
5
9
8
2J  
2K  
2Q  
2Q  
FF 2  
2CP  
GND = 11  
= 4  
6
2R  
V
CC  
TRUTH TABLE  
INPUTS  
OUTPUTS  
R
CP  
X
↓
J
X
L
K
Q
Q
L
X
L
L
H
H
No Change  
↓
H
H
L
L
H
L
L
↓
H
H
H
X
H
↓
H
H
X
Toggle  
H
H
No Change  
H =High Level (Steady State)  
L
X
↓
=Low Level (Steady State)  
= Irrelevant  
= High-to-Low Transition  
Logic Diagram  
14 (7)  
3(10)  
J
12 (9)  
Q
J
K
K
CL  
CL  
1 (5)  
2 (6)  
13 (8)  
Q
A  
CP  
R
R
2
CD54HC73, CD74HC73, CD74HCT73  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
CC  
DC Input Diode Current, I  
JA  
IK  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .  
80  
86  
For V < -0.5V or V > V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
I
I
CC  
o
DC Drain Current, per Output, I  
O
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
o
For -0.5V < V < V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA  
O
CC  
o
o
DC Output Diode Current, I  
OK  
For V < -0.5V or V > V  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
DC Output Source or Sink Current per Output Pin, I  
O
(SOIC - Lead Tips Only)  
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA  
CC  
CC  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
HC TYPES  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
High Level Input  
Voltage  
V
-
-
-
2
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
4.5  
3.15  
-
-
3.15  
-
-
3.15  
6
2
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
-0.02  
2
1.9  
1.9  
1.9  
OH  
IH  
V
IL  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
IH  
V
IL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
3
CD54HC73, CD74HC73, CD74HCT73  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
4
-
40  
-
80  
µA  
CC  
CC  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
V
V
or  
IH  
-0.02  
4.5  
4.4  
4.4  
4.4  
OH  
V
IL  
CMOS Loads  
High Level Output  
Voltage  
-4  
4.5  
3.98  
-
-
3.84  
-
3.7  
-
V
TTL Loads  
Low Level Output  
Voltage CMOS Loads  
V
V
V
or  
IH  
0.02  
4
4.5  
4.5  
-
-
-
-
0.1  
-
-
0.1  
-
-
0.1  
0.4  
V
V
OL  
IL  
Low Level Output  
Voltage  
0.26  
0.33  
TTL Loads  
Input Leakage  
Current  
I
V
and  
GND  
-
5.5  
5.5  
-
±0.1  
-
±1  
-
±1  
µA  
I
CC  
Quiescent Device  
Current  
I
V
or  
0
-
-
-
-
4
-
-
40  
-
-
80  
µA  
µA  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note 2)  
V
4.5 to  
5.5  
100  
360  
450  
490  
CC  
- 2.1  
NOTE:  
2. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
HC TYPES  
HCT TYPES  
3V  
INPUT  
All  
UNIT LOADS  
Input Level  
V
0.3  
CC  
V
S
50% V  
CC  
1.3V  
NOTE: Unit Load is ∆I  
tions table, e.g., 360µA max at 25 C.  
limit specified in DC Electrical Specifica-  
CC  
o
NOTE: Transition times and propagation delay times  
Prerequisite For Switching Specifications  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
CP Pulse Width  
t
t
-C = 50pF  
2
80  
16  
14  
80  
16  
14  
-
-
-
-
-
-
-
-
-
-
-
-
100  
20  
-
-
-
-
-
-
120  
24  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
w
L
4.5  
6
17  
20  
R Pulse Width  
-C = 50pF  
2
100  
20  
120  
24  
w
L
4.5  
6
17  
20  
4
CD54HC73, CD74HC73, CD74HCT73  
Prerequisite For Switching Specifications (Continued)  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
100  
20  
17  
3
MAX  
MIN  
120  
24  
20  
3
MAX  
UNITS  
ns  
Setup Time, J, K to CP  
t
C = 50pF  
2
4.5  
6
80  
16  
14  
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SU  
L
ns  
-
ns  
Hold Time, J, K to CP  
Removal Time  
t
C = 50pF  
2
-
ns  
H
L
4.5  
6
3
-
3
3
ns  
3
-
3
3
ns  
t
-C = 50pF  
2
80  
16  
14  
6
-
100  
20  
17  
5
120  
24  
20  
4
ns  
REM  
L
4.5  
6
-
ns  
-
ns  
CP Frequency  
f
C = 50pF  
2
-
MHz  
MHz  
MHz  
MHz  
MAX  
L
4.5  
5
30  
-
-
25  
-
20  
-
C = 15pF  
60  
-
L
C = 50pF  
6
35  
29  
23  
L
HCT TYPES  
CP Pulse Width  
t
t
C = 50pF  
L
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
5
16  
18  
16  
3
-
-
-
-
-
-
-
-
-
20  
23  
20  
3
-
-
-
-
-
-
-
24  
27  
24  
3
-
-
-
-
-
-
-
ns  
ns  
w
R Pulse Width  
CL = 50pF  
CL = 50pF  
CL = 50pF  
CL = 50pF  
CL = 50pF  
CL = 15pF  
w
Setup Time, J, K to CP  
Hold Time, J, K to CP  
Removal Time  
t
-
ns  
SU  
t
-
ns  
H
t
12  
30  
-
-
15  
25  
-
18  
20  
-
ns  
REM  
CP Frequency  
f
-
MHz  
MHz  
MAX  
60  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
Propagation Delay,  
CP to Q  
t
t
t
, t  
C = 50pF  
L
2
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
160  
32  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200  
40  
-
-
-
240  
48  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PLH PHL  
CL = 15pF  
13  
-
-
C = 50pF  
6
28  
160  
32  
-
34  
200  
40  
-
-
41  
240  
48  
-
L
Propagation Delay,  
CP to Q  
, t  
PLH PHL  
C = 50pF  
2
-
-
L
4.5  
5
-
-
C = 15pF  
13  
-
-
L
C = 50pF  
6
28  
145  
29  
-
34  
180  
36  
-
-
41  
220  
44  
-
L
Propagation Delay,  
R to Q, Q  
, t  
PLH PHL  
C = 50pF  
2
-
-
L
4.5  
5
-
-
C = 15pF  
12  
-
-
L
C = 50pF  
6
25  
75  
15  
13  
31  
95  
19  
16  
-
38  
110  
22  
19  
L
Output Transition Time  
t
, t  
TLH THL  
C = 50pF  
2
-
18  
-
L
4.5  
6
-
-
-
5
CD54HC73, CD74HC73, CD74HCT73  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
Input Capacitance  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
10  
-
MIN  
MAX  
10  
-
UNITS  
pF  
C
-
-
-
-
-
-
10  
-
-
-
-
-
I
Power Dissipation Capacitance  
(Notes 3, 4)  
C
5
28  
pF  
PD  
HCT TYPES  
Propagation Delay,  
CP to Q  
t
t
t
, t  
C = 50pF  
L
4.5  
4.5  
4.5  
-
-
-
-
-
-
38  
36  
34  
-
-
-
48  
45  
43  
-
-
-
57  
54  
51  
ns  
ns  
ns  
PLH PHL  
Propagation Delay,  
CP to Q  
, t  
PLH PHL  
CL = 50pF  
CL = 50pF  
Propagation Delay,  
R to Q, Q  
, t  
PLH PHL  
Output Transition Time  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
L
4.5  
-
-
-
-
-
-
15  
10  
-
-
-
-
19  
10  
-
-
-
-
22  
10  
-
ns  
pF  
pF  
C
-
-
I
Power Dissipation Capacitance  
(Notes 3, 4)  
C
5
28  
PD  
NOTES:  
3. C  
is used to determine the dynamic power consumption, per flip-flop.  
PD  
4. P = C  
2
2
V
f + Σ C V  
f where f = input frequency, f = output frequency, C = output load capacitance, V  
= supply voltage.  
D
PD CC  
i
L
CC  
o
i
o
L
CC  
Test Circuits and Waveforms  
I
t
+ t =  
WH  
WL  
I
t C = 6ns  
fC  
r
L
t
+ t  
=
L
WL  
WH  
t C = 6ns  
t C  
f
L
f
t C  
f
L
CL  
r
L
3V  
V
CC  
90%  
10%  
2.7V  
CLOCK  
CLOCK  
50%  
10%  
1.3V  
0.3V  
50%  
t
50%  
1.3V  
t
1.3V  
0.3V  
GND  
GND  
t
t
WH  
WL  
WH  
WL  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
CC  
CC  
CC  
CC  
accordance with device truth table. For f  
, input duty cycle = 50%.  
accordance with device truth table. For f  
, input duty cycle = 50%.  
MAX  
MAX  
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
t = 6ns  
t = 6ns  
t = 6ns  
t = 6ns  
r
f
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 4. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
6
CD54HC73, CD74HC73, CD74HCT73  
Test Circuits and Waveforms (Continued)  
t C  
t C  
t C  
t C  
r
L
f
L
f
L
r
L
V
3V  
CC  
90%  
10%  
2.7V  
0.3V  
CLOCK  
INPUT  
CLOCK  
INPUT  
50%  
1.3V  
GND  
GND  
t
t
t
t
H(L)  
H(H)  
H(H)  
H(L)  
V
3V  
CC  
DATA  
INPUT  
DATA  
INPUT  
50%  
1.3V  
t
SU(L)  
1.3V  
1.3V  
GND  
GND  
t
t
t
SU(H)  
SU(H)  
SU(L)  
t
t
90%  
50%  
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
90%  
1.3V  
OUTPUT  
OUTPUT  
10%  
10%  
t
t
t
PLH  
t
PHL  
PHL  
PLH  
t
REM  
t
REM  
V
3V  
CC  
SET, RESET  
OR PRESET  
SET, RESET  
OR PRESET  
50%  
1.3V  
GND  
GND  
IC  
IC  
C
C
L
L
50pF  
50pF  
FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
7
PACKAGE OPTION ADDENDUM  
www.ti.com  
17-Dec-2021  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
5962-8515301CA  
CD54HC73F  
ACTIVE  
CDIP  
CDIP  
CDIP  
J
J
J
14  
14  
14  
1
Non-RoHS  
& Green  
SNPB  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
-55 to 125  
-55 to 125  
-55 to 125  
5962-8515301CA  
CD54HC73F3A  
ACTIVE  
ACTIVE  
1
Non-RoHS  
& Green  
SNPB  
SNPB  
CD54HC73F  
CD54HC73F3A  
1
Non-RoHS  
& Green  
5962-8515301CA  
CD54HC73F3A  
CD74HC73E  
CD74HC73EE4  
CD74HC73M  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
PDIP  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
N
N
D
D
D
N
N
D
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
25  
25  
50  
RoHS & Green  
RoHS & Green  
RoHS & Green  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
NIPDAU  
N / A for Pkg Type  
N / A for Pkg Type  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
N / A for Pkg Type  
N / A for Pkg Type  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-40 to 125  
CD74HC73E  
CD74HC73E  
HC73M  
CD74HC73M96  
CD74HC73MT  
CD74HCT73E  
CD74HCT73EE4  
CD74HCT73M  
CD74HCT73M96  
2500 RoHS & Green  
HC73M  
250  
25  
RoHS & Green  
RoHS & Green  
RoHS & Green  
RoHS & Green  
HC73M  
CD74HCT73E  
CD74HCT73E  
HCT73M  
25  
50  
2500 RoHS & Green  
HCT73M  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
17-Dec-2021  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF CD54HC73, CD74HC73 :  
Catalog : CD74HC73  
•
Military : CD54HC73  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Military - QML certified for Military and Defense Applications  
•
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
18-Dec-2021  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
CD74HC73M96  
CD74HC73MT  
CD74HCT73M96  
SOIC  
SOIC  
SOIC  
D
D
D
14  
14  
14  
2500  
250  
330.0  
330.0  
330.0  
16.4  
16.4  
16.4  
6.5  
6.5  
6.5  
9.0  
9.0  
9.0  
2.1  
2.1  
2.1  
8.0  
8.0  
8.0  
16.0  
16.0  
16.0  
Q1  
Q1  
Q1  
2500  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
18-Dec-2021  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
CD74HC73M96  
CD74HC73MT  
CD74HCT73M96  
SOIC  
SOIC  
SOIC  
D
D
D
14  
14  
14  
2500  
250  
853.0  
210.0  
853.0  
449.0  
185.0  
449.0  
35.0  
35.0  
35.0  
2500  
Pack Materials-Page 2  
PACKAGE OUTLINE  
J0014A  
CDIP - 5.08 mm max height  
S
C
A
L
E
0
.
9
0
0
CERAMIC DUAL IN LINE PACKAGE  
4X .005 MIN  
[0.13]  
PIN 1 ID  
(OPTIONAL)  
A
.015-.060 TYP  
[0.38-1.52]  
1
14  
12X .100  
[2.54]  
14X .014-.026  
[0.36-0.66]  
14X .045-.065  
[1.15-1.65]  
.010 [0.25] C A B  
.754-.785  
[19.15-19.94]  
8
7
B
.245-.283  
[6.22-7.19]  
.2 MAX TYP  
[5.08]  
.13 MIN TYP  
[3.3]  
SEATING PLANE  
C
.308-.314  
[7.83-7.97]  
AT GAGE PLANE  
.015 GAGE PLANE  
[0.38]  
0 -15  
TYP  
14X .008-.014  
[0.2-0.36]  
4214771/A 05/2017  
NOTES:  
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for  
reference only. Dimensioning and tolerancing per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This package is hermitically sealed with a ceramic lid using glass frit.  
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.  
5. Falls within MIL-STD-1835 and GDIP1-T14.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
J0014A  
CDIP - 5.08 mm max height  
CERAMIC DUAL IN LINE PACKAGE  
(.300 ) TYP  
[7.62]  
SEE DETAIL B  
14  
SEE DETAIL A  
1
12X (.100 )  
[2.54]  
SYMM  
14X ( .039)  
[1]  
8
7
SYMM  
LAND PATTERN EXAMPLE  
NON-SOLDER MASK DEFINED  
SCALE: 5X  
.002 MAX  
[0.05]  
ALL AROUND  
(.063)  
[1.6]  
METAL  
(
.063)  
[1.6]  
SOLDER MASK  
OPENING  
METAL  
.002 MAX  
[0.05]  
ALL AROUND  
SOLDER MASK  
OPENING  
(R.002 ) TYP  
[0.05]  
DETAIL A  
DETAIL B  
SCALE: 15X  
13X, SCALE: 15X  
4214771/A 05/2017  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license  
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you  
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these  
resources.  
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for  
TI products.  
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2021, Texas Instruments Incorporated  

相关型号：

CD54HC74

 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger
TI

CD54HC74E

 Logic IC
ETC

CD54HC74EN

 Logic IC
ETC

CD54HC74F

 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger
TI

CD54HC74F/3

 HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
RENESAS

CD54HC74F3A

 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger
TI

CD54HC74F3A

 IC,FLIP-FLOP,DUAL,D TYPE,HC-CMOS,DIP,14PIN,CERAMIC
RENESAS

CD54HC74H

 CD54HC74H
RENESAS

CD54HC74H/3

 HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14
RENESAS

CD54HC74H/3A

 HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14
RENESAS

CD54HC74M

 Logic IC
ETC

CD54HC75

 Dual 2-Bit Bistable Transparent Latch
TI
©2020 ICPDF网 联系我们和版权申明