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CD54HC73 [TI]

Dual J-K Flip-Flop with Reset Negative-Edge Trigger; 双JK触发器与复位负边沿触发
CD54HC73
型号： CD54HC73
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Dual J-K Flip-Flop with Reset Negative-Edge Trigger
双JK触发器与复位负边沿触发

触发器
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中文：  中文翻译
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CD54HC73, CD74HC73,  
CD74HCT73  
Data sheet acquired from Harris Semiconductor  
SCHS134E  
Dual J-K Flip-Flop with Reset  
Negative-Edge Trigger  
February 1998 - Revised September 2003  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise  
Immunity and Increased Input Rise and Fall Times  
The ’HC73 and CD74HCT73 utilize silicon gate CMOS  
technology to achieve operating speeds equivalent to LSTTL  
parts. They exhibit the low power consumption of standard  
CMOS integrated circuits, together with the ability to drive 10  
LSTTL loads.  
[ /Title  
(CD74  
HC73,  
CD74  
HCT73  
)
• Asynchronous Reset  
• Complementary Outputs  
• Buffered Inputs  
These flip-flops have independent J, K, Reset and Clock  
inputs and Q and Q outputs. They change state on the  
negative-going transition of the clock pulse. Reset is  
accomplished asynchronously by a low level input. This  
device is functionally identical to the HC/HCT107 but differs  
in terminal assignment and in some parametric limits.  
• Typical f  
MAX  
= 60MHz at V = 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
/Sub-  
ject  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
(Dual  
J-K  
Flip-  
Flop  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The HCT logic family is functionally as well as pin compatible  
with the standard LS logic family.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
PART NUMBER  
CD54HC73F3A  
CD74HC73E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC73M  
at V  
= 5V  
CC  
CD74HC73MT  
CD74HC73M96  
CD74HCT73E  
CD74HCT73M  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC73 (CERDIP)  
CD74HC73, CD74HCT73 (PDIP, SOIC)  
TOP VIEW  
1CP  
1R  
1
2
3
4
5
6
7
14 1J  
13 1Q  
12 1Q  
11 GND  
10 2K  
1K  
V
CC  
2CP  
2R  
9
8
2Q  
2Q  
2J  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD54HC73, CD74HC73, CD74HCT73  
Functional Diagram  
14  
12  
1J  
1Q  
3
FF 1  
13  
1K  
1Q  
1
2
1CP  
1R  
7
10  
5
9
8
2J  
2K  
2Q  
2Q  
FF 2  
2CP  
GND = 11  
= 4  
6
2R  
V
CC  
TRUTH TABLE  
INPUTS  
OUTPUTS  
R
CP  
X
↓
J
X
L
K
Q
Q
L
X
L
L
H
H
No Change  
↓
H
H
L
L
H
L
L
↓
H
H
H
X
H
↓
H
H
X
Toggle  
H
H
No Change  
H =High Level (Steady State)  
L
X
↓
=Low Level (Steady State)  
= Irrelevant  
= High-to-Low Transition  
Logic Diagram  
14 (7)  
3(10)  
J
12 (9)  
Q
J
K
K
CL  
CL  
1 (5)  
2 (6)  
13 (8)  
Q
A  
CP  
R
R
2
CD54HC73, CD74HC73, CD74HCT73  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
CC  
DC Input Diode Current, I  
JA  
IK  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .  
80  
86  
For V < -0.5V or V > V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
I
I
CC  
o
DC Drain Current, per Output, I  
O
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
o
For -0.5V < V < V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA  
O
CC  
o
o
DC Output Diode Current, I  
OK  
For V < -0.5V or V > V  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
DC Output Source or Sink Current per Output Pin, I  
O
(SOIC - Lead Tips Only)  
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA  
CC  
CC  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
HC TYPES  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
High Level Input  
Voltage  
V
-
-
-
2
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
4.5  
3.15  
-
-
3.15  
-
-
3.15  
6
2
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
-0.02  
2
1.9  
1.9  
1.9  
OH  
IH  
V
IL  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
IH  
V
IL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
3
CD54HC73, CD74HC73, CD74HCT73  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
4
-
40  
-
80  
µA  
CC  
CC  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
V
V
or  
IH  
-0.02  
4.5  
4.4  
4.4  
4.4  
OH  
V
IL  
CMOS Loads  
High Level Output  
Voltage  
-4  
4.5  
3.98  
-
-
3.84  
-
3.7  
-
V
TTL Loads  
Low Level Output  
Voltage CMOS Loads  
V
V
V
or  
IH  
0.02  
4
4.5  
4.5  
-
-
-
-
0.1  
-
-
0.1  
-
-
0.1  
0.4  
V
V
OL  
IL  
Low Level Output  
Voltage  
0.26  
0.33  
TTL Loads  
Input Leakage  
Current  
I
V
and  
GND  
-
5.5  
5.5  
-
±0.1  
-
±1  
-
±1  
µA  
I
CC  
Quiescent Device  
Current  
I
V
or  
0
-
-
-
-
4
-
-
40  
-
-
80  
µA  
µA  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note 2)  
V
4.5 to  
5.5  
100  
360  
450  
490  
CC  
- 2.1  
NOTE:  
2. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
HC TYPES  
HCT TYPES  
3V  
INPUT  
All  
UNIT LOADS  
Input Level  
V
0.3  
CC  
V
S
50% V  
CC  
1.3V  
NOTE: Unit Load is ∆I  
tions table, e.g., 360µA max at 25 C.  
limit specified in DC Electrical Specifica-  
CC  
o
NOTE: Transition times and propagation delay times  
Prerequisite For Switching Specifications  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
CP Pulse Width  
t
t
-C = 50pF  
2
80  
16  
14  
80  
16  
14  
-
-
-
-
-
-
-
-
-
-
-
-
100  
20  
-
-
-
-
-
-
120  
24  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
w
L
4.5  
6
17  
20  
R Pulse Width  
-C = 50pF  
2
100  
20  
120  
24  
w
L
4.5  
6
17  
20  
4
CD54HC73, CD74HC73, CD74HCT73  
Prerequisite For Switching Specifications (Continued)  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
100  
20  
17  
3
MAX  
MIN  
120  
24  
20  
3
MAX  
UNITS  
ns  
Setup Time, J, K to CP  
t
C = 50pF  
2
4.5  
6
80  
16  
14  
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SU  
L
ns  
-
ns  
Hold Time, J, K to CP  
Removal Time  
t
C = 50pF  
2
-
ns  
H
L
4.5  
6
3
-
3
3
ns  
3
-
3
3
ns  
t
-C = 50pF  
2
80  
16  
14  
6
-
100  
20  
17  
5
120  
24  
20  
4
ns  
REM  
L
4.5  
6
-
ns  
-
ns  
CP Frequency  
f
C = 50pF  
2
-
MHz  
MHz  
MHz  
MHz  
MAX  
L
4.5  
5
30  
-
-
25  
-
20  
-
C = 15pF  
60  
-
L
C = 50pF  
6
35  
29  
23  
L
HCT TYPES  
CP Pulse Width  
t
t
C = 50pF  
L
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
5
16  
18  
16  
3
-
-
-
-
-
-
-
-
-
20  
23  
20  
3
-
-
-
-
-
-
-
24  
27  
24  
3
-
-
-
-
-
-
-
ns  
ns  
w
R Pulse Width  
CL = 50pF  
CL = 50pF  
CL = 50pF  
CL = 50pF  
CL = 50pF  
CL = 15pF  
w
Setup Time, J, K to CP  
Hold Time, J, K to CP  
Removal Time  
t
-
ns  
SU  
t
-
ns  
H
t
12  
30  
-
-
15  
25  
-
18  
20  
-
ns  
REM  
CP Frequency  
f
-
MHz  
MHz  
MAX  
60  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
Propagation Delay,  
CP to Q  
t
t
t
, t  
C = 50pF  
L
2
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
160  
32  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200  
40  
-
-
-
240  
48  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PLH PHL  
CL = 15pF  
13  
-
-
C = 50pF  
6
28  
160  
32  
-
34  
200  
40  
-
-
41  
240  
48  
-
L
Propagation Delay,  
CP to Q  
, t  
PLH PHL  
C = 50pF  
2
-
-
L
4.5  
5
-
-
C = 15pF  
13  
-
-
L
C = 50pF  
6
28  
145  
29  
-
34  
180  
36  
-
-
41  
220  
44  
-
L
Propagation Delay,  
R to Q, Q  
, t  
PLH PHL  
C = 50pF  
2
-
-
L
4.5  
5
-
-
C = 15pF  
12  
-
-
L
C = 50pF  
6
25  
75  
15  
13  
31  
95  
19  
16  
-
38  
110  
22  
19  
L
Output Transition Time  
t
, t  
TLH THL  
C = 50pF  
2
-
18  
-
L
4.5  
6
-
-
-
5
CD54HC73, CD74HC73, CD74HCT73  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
Input Capacitance  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
10  
-
MIN  
MAX  
10  
-
UNITS  
pF  
C
-
-
-
-
-
-
10  
-
-
-
-
-
I
Power Dissipation Capacitance  
(Notes 3, 4)  
C
5
28  
pF  
PD  
HCT TYPES  
Propagation Delay,  
CP to Q  
t
t
t
, t  
C = 50pF  
L
4.5  
4.5  
4.5  
-
-
-
-
-
-
38  
36  
34  
-
-
-
48  
45  
43  
-
-
-
57  
54  
51  
ns  
ns  
ns  
PLH PHL  
Propagation Delay,  
CP to Q  
, t  
PLH PHL  
CL = 50pF  
CL = 50pF  
Propagation Delay,  
R to Q, Q  
, t  
PLH PHL  
Output Transition Time  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
L
4.5  
-
-
-
-
-
-
15  
10  
-
-
-
-
19  
10  
-
-
-
-
22  
10  
-
ns  
pF  
pF  
C
-
-
I
Power Dissipation Capacitance  
(Notes 3, 4)  
C
5
28  
PD  
NOTES:  
3. C  
is used to determine the dynamic power consumption, per flip-flop.  
PD  
4. P = C  
2
2
V
f + Σ C V  
f where f = input frequency, f = output frequency, C = output load capacitance, V  
= supply voltage.  
D
PD CC  
i
L
CC  
o
i
o
L
CC  
Test Circuits and Waveforms  
I
t
+ t =  
WH  
WL  
I
t C = 6ns  
fC  
r
L
t
+ t  
=
L
WL  
WH  
t C = 6ns  
t C  
f
L
f
t C  
f
L
CL  
r
L
3V  
V
CC  
90%  
10%  
2.7V  
CLOCK  
CLOCK  
50%  
10%  
1.3V  
0.3V  
50%  
t
50%  
1.3V  
t
1.3V  
0.3V  
GND  
GND  
t
t
WH  
WL  
WH  
WL  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
CC  
CC  
CC  
CC  
accordance with device truth table. For f  
, input duty cycle = 50%.  
accordance with device truth table. For f  
, input duty cycle = 50%.  
MAX  
MAX  
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
t = 6ns  
t = 6ns  
t = 6ns  
t = 6ns  
r
f
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 4. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
6
CD54HC73, CD74HC73, CD74HCT73  
Test Circuits and Waveforms (Continued)  
t C  
t C  
t C  
t C  
r
L
f
L
f
L
r
L
V
3V  
CC  
90%  
10%  
2.7V  
0.3V  
CLOCK  
INPUT  
CLOCK  
INPUT  
50%  
1.3V  
GND  
GND  
t
t
t
t
H(L)  
H(H)  
H(H)  
H(L)  
V
3V  
CC  
DATA  
INPUT  
DATA  
INPUT  
50%  
1.3V  
t
SU(L)  
1.3V  
1.3V  
GND  
GND  
t
t
t
SU(H)  
SU(H)  
SU(L)  
t
t
90%  
50%  
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
90%  
1.3V  
OUTPUT  
OUTPUT  
10%  
10%  
t
t
t
PLH  
t
PHL  
PHL  
PLH  
t
REM  
t
REM  
V
3V  
CC  
SET, RESET  
OR PRESET  
SET, RESET  
OR PRESET  
50%  
1.3V  
GND  
GND  
IC  
IC  
C
C
L
L
50pF  
50pF  
FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
7
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
CDIP  
PDIP  
Drawing  
5962-8515301CA  
CD54HC73F  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
J
J
14  
14  
14  
14  
1
1
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Level-NC-NC-NC  
Level-NC-NC-NC  
Level-NC-NC-NC  
CD54HC73F3A  
CD74HC73E  
J
1
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD74HC73EE4  
CD74HC73M  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SOIC  
SOIC  
N
D
D
D
D
D
D
N
N
D
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC73M96  
CD74HC73M96E4  
CD74HC73ME4  
CD74HC73MT  
CD74HC73MTE4  
CD74HCT73E  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
CD74HCT73EE4  
CD74HCT73M  
CD74HCT73ME4  
25  
Pb-Free  
(RoHS)  
CU NIPDAU Level-NC-NC-NC  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Sep-2005  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
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Use of such information may require a license from a third party under the patents or other intellectual property  
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