CD54HCT04W [TI]
High Speed CMOS Logic Hex Inverter; 高速CMOS逻辑六反相器
| 型号： | CD54HCT04W |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Hex Inverter |
| 文件： | 总6页 (文件大小：33K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC04, CD54HCT04,
CD74HC04, CD74HCT04
Data sheet acquired from Harris Semiconductor
SCHS117
High Speed CMOS Logic Hex Inverter
August 1997
Features
Description
• Buffered Inputs
The Harris CD54HC04, CD54HCT04, CD74HC04 and
CD74HCT04 logic gates utilize silicon gate CMOS technol-
ogy to achieve operating speeds similar to LSTTL gates with
the low power consumption of standard CMOS integrated
circuits. All devices have the ability to drive 10 LSTTL loads.
The 74HCT logic family is functionally pin compatible with
the standard 74LS logic family.
• Typical Propagation Delay: 6ns at V
o
= 5V,
[ /Title
(CD54H
C04,
CC
C = 15pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
CD54H
CT04,
CD74H
C04,
CD74H
CT04)
/Subject
(High
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
TEMP. RANGE
PKG.
NO.
o
PART NUMBER
CD74HC04E
CD74HCT04E
CD74HC04M
CD74HCT04M
CD54HC04F
CD54HCT04F
CD54HC04W
CD54HCT04W
CD54HC04H
CD54HCT04H
NOTE:
( C)
PACKAGE
14 Ld PDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
• Significant Power Reduction Compared to LSTTL
Logic ICs
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E14.3
• HC Types
E14.3
- 2V to 6V Operation
Speed
M14.15
M14.15
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
• HCT Types
14 Ld CERDIP F14.3
- 4.5V to 5.5V Operation
14 Ld CERDIP F14.3
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
Wafer
Wafer
Die
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Die
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
Pinout
CD54HC04, CD54HCT04, CD74HC04, CD74HCT04
(PDIP, CERDIP, SOIC)
TOP VIEW
1A
1Y
1
2
3
4
5
6
7
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
2A
2Y
3A
3Y
9
8
4A
4Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1471.1
Copyright © Harris Corporation 1997
1
CD54HC04, CD54HCT04, CD74HC04, CD74HCT04
Functional Diagram
14
13
12
11
10
9
1
2
3
4
5
6
7
V
1A
1Y
CC
6A
6Y
5A
5Y
4A
4Y
2A
2Y
3A
3Y
8
GND
TRUTH TABLE
INPUTS
nA
L
nY
H
L
H
NOTE: H = High Voltage Level, L = Low Voltage Level
Logic Symbol
nA
nY
2
CD54HC04, CD54HCT04, CD74HC04, CD74HCT04
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 2)
θ
( C/W)
θ
( C/W)
CC
DC Input Diode Current, I
JA
JC
PDIP Package . . . . . . . . . . . . . . . . . . .
CERDIP Package . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
100
130
180
N/A
55
N/A
IK
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
o
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
o
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO +85 C -55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
4.5
3.15
-
-
3.15
-
-
3.15
6
2
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
1.9
1.9
OH
IH
V
IL
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
IH
V
IL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD54HC04, CD54HCT04, CD74HC04, CD74HCT04
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO +85 C -55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Quiescent Device
Current
I
V
GND
or
0
6
-
-
2
-
20
-
40
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
5.5
5.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
Low Level Output
Voltage
CMOS Loads
V
V
or
IH
0.02
4
-
-
-
0.1
-
-
-
0.1
0.33
±1
-
-
-
0.1
0.4
±1
OL
V
IL
Low Level Output
Voltage
TTL Loads
0.26
±0.1
V
Input Leakage
Current
I
V
0
µA
I
CC
and
GND
Quiescent Device
Current
I
V
or
0
-
-
-
-
2
-
-
20
-
-
40
µA
µA
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note)
∆I
V
4.5 to
5.5
100
360
450
490
CC
CC
- 2.1
NOTE: For dual-supply systems theorectical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
nB
UNIT LOADS
1.2
NOTE: Unit Load is ∆I
Specifications table, e.g. 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Propagation Delay,
Input to Output (Figure 1)
t
, t
PLH PHL
C = 50pF
2
4.5
6
-
-
-
-
-
-
85
7
-
-
-
-
105
21
18
-
-
-
-
-
130
67
22
-
ns
ns
ns
ns
L
-
14
-
Propagation Delay, Data Input to
Output Y
t , t
PLH PHL
C = 15pF
5
6
L
4
CD54HC04, CD54HCT04, CD74HC04, CD74HCT04
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
95
19
16
10
-
MIN
MAX
110
22
UNITS
ns
Transition Times (Figure 1)
t
, t
TLH THL
C = 50pF
L
2
4.5
6
-
-
-
-
-
-
-
75
15
13
10
-
-
-
-
-
-
18
-
ns
-
-
19
ns
Input Capacitance
C
-
-
-
-
-
10
pF
I
Power Dissipation Capacitance
(Notes 3, 4)
C
5
21
-
-
pF
PD
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
t
, t
PLH PHL
C = 50pF
4.5
5
-
-
-
19
-
-
-
24
-
-
-
29
-
ns
ns
L
Propagation Delay, Data Input to
Output Y
t , t
PLH PHL
C = 15pF
7
L
Transition Times (Figure 2)
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
-
-
-
-
-
15
10
-
-
-
-
19
10
-
-
-
-
22
10
-
ns
pF
pF
C
-
-
I
Power Dissipation Capacitance
(Notes 3, 4)
C
5
24
PD
NOTES:
3. C
PD
is used to determine the dynamic power consumption, per gate.
2
4. P = V
CC
f (C
PD
+ C ) where f = input frequency, C = output load capacitance, V = supply voltage.
CC
D
i
L
i
L
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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