CD54HCT166 [TI]
High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register; 高速CMOS逻辑8位并行输入/串行输出移位寄存器
| 型号： | CD54HCT166 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register |
| 文件： | 总13页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC166, CD74HC166,
CD54HCT166, CD74HCT166
Data sheet acquired from Harris Semiconductor
SCHS157C
High-Speed CMOS Logic
8-Bit Parallel-In/Serial-Out Shift Register
February 1998 - Revised October 2003
Features
Description
• Buffered Inputs
The ’HC166 and ’HCT166 8-bit shift register is fabricated
with silicon gate CMOS technology. It possesses the low
power consumption of standard CMOS integrated circuits,
and can operate at speeds comparable to the equivalent low
power Schottky device.
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
[ /Title
(CD74
HC166
,
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
The ’HCT166 is functionally and pin compatible with the
standard ’LS166.
CD74
HCT16
6)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Bit
Paral-
lel-
• Significant Power Reduction Compared to LSTTL
Logic ICs
The 166 is an 8-bit shift register that has fully synchronous
serial or parallel data entry selected by an active LOW Parallel
Enable (PE) input. When the PE is LOW one setup time before
the LOW-to-HIGH clock transition, parallel data is entered into
the register. When PE is HIGH, data is entered into the internal
bit position Q0 from Serial Data Input (DS), and the remaining
bits are shifted one place to the right (Q0 → Q1 → Q2, etc.)
with each positive-going clock transition. For expansion of the
register in parallel to serial converters, the Q7 output is con-
nected to the DS input of the succeeding stage.
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
• HCT Types
= 5V
CC
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL
IH
The clock input is a gated OR structure which allows one
input to be used as an active LOW Clock Enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary and
can be reversed for layout convenience. The LOW-to-HIGH
transition of CE input should only take place while the CP is
HIGH for predictable operation.
Pinout
CD54HC166, CD54HCT166
(CERDIP)
CD74HC166, CD74HCT166
(PDIP, SOIC)
In/Seri
A LOW on the Master Reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all bit
positions to a LOW state.
TOP VIEW
DS
D0
1
2
3
4
5
6
7
8
16 V
CC
15 PE
14 D7
13 Q7
12 D6
11 D5
10 D4
Ordering Information
D1
o
D2
PART NUMBER
CD54HC166F3A
CD54HCT166F3A
CD74HC166E
TEMP. RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
D3
CE
CP
9
MR
GND
CD74HC166M
CD74HC166MT
CD74HC166M96
CD74HCT166E
CD74HCT166M
CD74HCT166MT
CD74HCT166M96
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
Functional Diagram
D0 D1 D2 D3 D4 D5 D6 D7
PE
PARALLEL ENABLE CIRCUIT
D0
D7
D
S
8 - REGISTERS
Q7
CP
CE
MR
TRUTH TABLE
INPUTS
INTERNAL
Q STATES
PARALLEL
MASTER
RESET
PARALLEL
ENABLE
CLOCK
ENABLE
OUTPUT
Q7
CLOCK
SERIAL
D0 D7
Q0
L
Q1
L
L
X
X
L
X
L
L
L
L
H
X
L
↑
↑
↑
↑
X
X
X
H
L
X
X
L
H
H
H
H
H
Q00
a
Q10
b
Q0
h
a...h
X
H
H
X
H
Q0n
Q0n
Q10
Q6n
Q6n
Q70
X
L
X
X
Q00
H= High Voltage Level
L= Low Voltage Level
X= Don’t Care
↑= Transition from Low to High Level
a...h = The level of steady-state input at inputs D0 thru D7, respectively.
Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established.
Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ↑ transition of the clock.
2
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
67
73
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
Input Leakage
Current
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
GND
3
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
V
or
IH
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
DS, D0-D7
0.2
0.35
0.5
PE
CP, CE
MR
0.2
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Clock Frequency
(Figure 1)
f
2
6
-
-
-
5
-
-
-
4
-
-
-
MHz
MHz
MHz
MAX
4.5
30
35
25
29
20
23
6
4
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
MR Pulse Width
SYMBOL
V
(V)
MIN
100
20
17
80
16
14
80
16
14
1
MAX
MIN
125
25
21
100
20
17
100
20
17
1
MAX
MIN
150
30
26
120
24
20
120
24
20
1
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CC
t
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
w
(Figure 1)
4.5
6
2
Clock Pulse Width
(Figure 1)
t
W
4.5
6
Set-up Time
Data and CE to Clock
(Figure 5)
t
2
SU
4.5
6
Hold Time
Data to Clock
(Figure 5)
t
2
H
4.5
6
1
1
1
1
1
1
Removal Time
MR to Clock
(Figure 5)
t
REM
2
0
0
0
4.5
6
0
0
0
0
0
0
Set-up Time
PE to CP
(Figure 5)
t
2
145
29
25
0
180
36
31
0
220
44
38
0
SU
4.5
6
Hold Time
PE to CP or CE
(Figure 5)
t
2
H
4.5
6
0
0
0
0
0
0
HCT TYPES
Clock Frequency (Figure 2)
f
MAX
4.5
4.5
4.5
4.5
25
35
20
16
-
-
-
-
20
44
25
20
-
-
-
-
16
53
30
24
-
-
-
-
MHz
ns
MR Pulse Width (Figure 2)
Clock Pulse Width (Figure 2)
t
w
w
t
ns
Set-up Time Data and CE to
Clock (Figure 6)
t
ns
SU
Hold Time Data to Clock
(Figure 6)
t
4.5
4.5
0
0
-
-
0
0
-
-
0
0
-
-
ns
ns
H
Removal Time MR to Clock
(Figure 6)
t
REM
Set-up Time PE to CP (Figure 6)
t
4.5
4.5
30
0
-
-
38
0
-
-
45
0
-
-
ns
ns
SU
Hold Time PE to CP or CE
(Figure 6)
t
H
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay,
Clock to Output (Figure 3)
t
, t
C = 50pF
2
-
-
160
32
-
200
40
-
240
48
-
ns
ns
ns
ns
PLH PHL
L
4.5
C = 15pF
L
5
6
13
-
CL = 50pF
27
34
41
5
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
MAX
-40 C TO 85 C -55 C TO 125 C
TEST
CONDITIONS
PARAMETER
SYMBOL
, t
V
(V)
TYP
MAX
95
19
16
200
40
34
10
-
MAX
110
22
UNITS
ns
CC
Output Transition Time
(Figure 3)
t
C = 50pF
2
-
-
75
15
13
160
32
27
10
-
TLH THL
L
4.5
ns
6
2
-
19
ns
Propagation Delay
MR to Output
(Figure 3)
t
C = 50pF
L
-
240
48
ns
PHL
4.5
6
-
ns
-
41
ns
Input Capacitance
C
-
-
-
-
10
pF
I
Power Dissipation
Capacitance
C
5
41
-
pF
PD
(Notes 3, 4)
HCT TYPES
Propagation Delay,
Clock to Output
(Figure 4)
t
, t
C = 50pF
4.5
-
40
50
60
ns
PLH PHL
L
Output Transition Time
(Figure 4)
t
, t
TLH THL
C = 50pF
4.5
4.5
-
-
-
-
15
40
10
19
50
10
22
60
10
ns
ns
pF
L
Propagation Delay
MR to Output (Figure 4)
t
C = 50pF
L
PHL
Input Capacitance
NOTES:
C
-
I
3. C
4. P
is used to determine the dynamic power consumption, per gate.
PD
2
2
C
V
f + ∑ (C V
+ f ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply
D = PD CC
i
L
CC
O
i
O
L
CC
Voltage.
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
f
t C
f
L
CL
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
6
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
Test Circuits and Waveforms (Continued)
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
PDIP
Drawing
CD54HC166F3A
CD54HCT166F3A
CD74HC166E
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
1
1
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC166EE4
CD74HC166M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
N
D
D
D
D
D
D
N
N
D
D
D
D
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC166M96
CD74HC166M96E4
CD74HC166ME4
CD74HC166MT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC166MTE4
CD74HCT166E
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT166EE4
CD74HCT166M
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT166M96
CD74HCT166M96E4
CD74HCT166ME4
CD74HCT166MT
CD74HCT166MTE4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Low Power Wireless www.ti.com/lpw
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated
相关型号：
CD54HCT166F
HCT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16
ROCHESTER
CD54HCT166F/3
HCT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16
RENESAS
CD54HCT166F/3A
IC HCT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, Shift Register
RENESAS
CD54HCT166H/3
HCT SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, UUC16
RENESAS
©2020 ICPDF网 联系我们和版权申明