CD54HCT374F3A [TI]
High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered; 高速CMOS逻辑八路D型触发器，三态上升沿触发
| 型号： | CD54HCT374F3A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered |
| 文件： | 总15页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54/74HC374, CD54/74HCT374,
CD54/74HC574, CD54/74HCT574
Data sheet acquired from Harris Semiconductor
SCHS183C
High-Speed CMOS Logic Octal D-Type Flip-Flop,
3-State Positive-Edge Triggered
February 1998 - Revised May 2004
Features
Description
• Buffered Inputs
The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-type
flip-flops with 3-state outputs and the capability to drive 15
• Common Three-State Output Enable Control
• Three-State Outputs
[ /Title
(CD74
HC374
,
LSTTL loads. The eight edge-triggered flip-flops enter data into
their registers on the LOW to HIGH transition of clock (CP). The
output enable (OE) controls the 3-state outputs and is
independent of the register operation. When OE is HIGH, the
outputs are in the high-impedance state. The 374 and 574 are
identical in function and differ only in their pinout arrangements.
• Bus Line Driving Capability
• Typical Propagation Delay (Clock to Q) = 15ns at
o
CD74
HCT37
4,
CD74
HC574
,
V
= 5V, C = 15pF, T = 25 C
L A
CC
• Fanout (Over Temperature Range)
Ordering Information
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
TEMP. RANGE
o
PART NUMBER
CD54HC374F3A
CD54HC574F3A
CD54HCT374F3A
CD54HCT574F3A
CD74HC374E
( C)
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
CD74
HCT57
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
CD74HC374M
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
- 2-V to 6-V Operation
CD74HC374M96
CD74HC574E
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
CD74HC574M
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
• HCT Types
CD74HC574M96
CD74HCT374E
CD74HCT374M
CD74HCT374M96
CD74HCT574E
CD74HCT574M
CD74HCT574M96
CD74HCT574PWR
- 4.5-V to 5.5-V Operation
- Direct LSTTL Input Logic Compatibility,
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes
96 and R denote tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
Pinouts
CD54HC574, CD54HCT574
(CERDIP)
CD54HC374, CD54HCT374
(CERDIP)
CD74HC574
(PDIP, SOIC)
CD74HC374, CD74HCT374
(PDIP, SOIC)
CD74HCT574
(PDIP, SOIC, TSSOP)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
9
V
1
2
3
4
5
6
7
8
9
V
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
20
19
OE
D0
D1
D2
D3
D4
D5
D6
D7
20
19
CC
CC
Q7
Q0
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12
12
Q4
Q7
GND 10
11 CP
GND 10
11 CP
Functional Diagram
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
D
D
D
D
D
D
D
D
CP
CP
CP
CP
CP
CP
CP
CP
Q
Q
Q
Q
Q
Q
Q
Q
CP
OE
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
TRUTH TABLE
INPUTS
OUTPUT
OE
L
CP
↑
Dn
H
L
Qn
H
L
↑
L
L
L
X
Q0
Z
H
X
X
H = High Level (Steady State)
L = Low Level (Steady State)
X= Don’t Care
↑= Transition from Low to High Level
Q0= The level of Q before the indicated steady-state input
conditions were established
Z = High Impedance State
2
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1). . . . . . . . . . . . . . . . . θ ( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
o
DC Drain Current, per Output, I
O
o
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
DC Output Source or Sink Current per Output Pin, I
O
(SOIC - Lead Tips Only)
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-6
4.5
6
3.98
-
3.84
-
3.7
-
-7.8
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
6
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
7.8
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
Three- State Leakage
Current
V
or V
V
=V
CC
-
6
-
-
±0.5
-
±5.0
-
±10
µA
IL
IH
O
or GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
6
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
6
-
-
-
-
±0.1
8
-
-
-
-
±1
80
-
-
-
-
±1
µA
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
-
160
±10
490
CC
CC
GND
Three- State Leakage
Current
V
or V
V
=V
±0.5
360
±5.0
450
IL
IH
O
CC
or GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
-
4.5 to
5.5
100
CC
-2.1
NOTE:
2. For dual-supply systems, theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
UNIT LOADS
INPUT
D0 - D7
CP
HCT374
0.3
HCT574
0.4
0.9
0.75
0.6
OE
1.3
NOTE: Unit Load is ∆I limit specific in DC Electrical Specifications
CC
o
Table, e.g., 360µA max. at 25 C.
4
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V) MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
Maximum Clock
Frequency
f
MAX
2
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
25
29
100
20
17
75
15
13
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20
23
120
24
20
90
18
15
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
4.5
6
30
35
80
16
14
60
12
10
5
Clock Pulse Width
t
2
W
4.5
6
ns
ns
Setup Time
Data to Clock
t
2
ns
SU
4.5
6
ns
ns
Hold Time
Data to Clock
t
2
ns
H
4.5
6
5
5
5
ns
5
5
5
ns
HCT TYPES
Maximum Clock
Frequency
f
MAX
4.5
30
-
-
25
-
-
20
-
-
MHz
Clock Pulse Width
t
4.5
4.5
16
12
-
-
-
-
20
15
-
-
-
-
24
18
-
-
-
-
ns
ns
W
Setup Time
t
SU
Data to Clock
Hold Time
t
4.5
5
-
-
5
-
-
5
-
-
ns
H
Data to Clock
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
Clock to Output
t
, t
C
= 50pF
PLH PHL
L
2
-
-
-
165
33
-
-
-
-
-
-
-
-
-
205
41
-
-
-
-
-
-
-
-
-
250
50
-
ns
ns
ns
ns
ns
ns
ns
ns
4.5
5
-
-
-
-
-
-
-
C
C
C
= 15pF
= 50pF
= 50pF
15
-
L
L
L
6
28
135
27
-
35
170
34
-
43
205
41
-
Output Disable to Q
t
, t
PLZ PHZ
2
-
4.5
5
-
C
C
= 15pF
= 50pF
11
-
L
6
23
29
35
L
5
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Output Enable to Q
t
, t
PZL PZH
C
= 50pF
2
-
-
-
150
30
-
-
-
-
-
-
-
-
-
-
-
190
38
-
-
-
-
-
-
-
-
-
-
-
225
45
-
ns
ns
L
4.5
5
-
-
C
C
C
C
= 15pF
= 50pF
= 15pF
= 50pF
12
-
ns
L
L
L
L
6
-
26
-
33
-
38
-
ns
Maximum Clock Frequency
Output Transition Time
f
5
-
60
-
MHz
ns
MAX
t
, t
2
-
60
12
10
10
20
75
15
13
10
20
90
18
15
10
20
THL TLH
4.5
6
-
-
ns
-
-
ns
Input Capacitance
C
C
C
= 50pF
-
-
10
20
-
pF
pF
I
L
Three-State Output
Capacitance
C
-
-
O
Power Dissipation Capacitance
(Notes 3, 4)
C
= 15pF
5
-
39
-
-
-
-
-
pF
PD
L
HCT TYPES
Propagation Delay
Clock to Output
t
t
PHL, PLH
C
C
C
C
C
C
C
C
C
= 50pF
= 15pF
= 50pF
= 15pF
= 50pF
= 15pF
= 15pF
= 50pF
= 50pF
-
4.5
5
-
-
-
15
-
33
-
-
-
-
-
-
-
-
-
-
-
41
-
-
-
-
-
-
-
-
-
-
-
50
-
ns
ns
L
L
L
L
L
L
L
L
L
Output Disable to Q
Output Enable to Q
t
t
, t
PLZ PHZ
4.5
5
-
28
-
35
-
42
-
ns
-
11
-
ns
, t
PZL PZH
4.5
5
-
30
-
38
-
45
-
ns
-
12
60
-
ns
Maximum Clock Frequency
Output Transition Time
Input Capacitance
f
5
-
-
-
-
MHz
ns
MAX
t
, t
4.5
-
-
12
10
20
15
10
20
18
10
20
TLH THL
C
10
20
-
pF
pF
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation Capacitance
(Notes 3, 4)
C
C
= 15pF
5
-
47
-
-
-
-
-
pF
PD
L
NOTES:
3. C
is used to determine the dynamic power consumption, per package.
PD
4. P = C
2
2
V
f + ∑ V
f
C where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply
CC
D
PD CC
i
CC
O
L
i
O
L
Voltage.
6
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574
Test Circuits and Waveforms (Continued)
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
8
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
CDIP
CDIP
CDIP
CDIP
PDIP
Drawing
5962-8974201RA
CD54HC374F3A
CD54HC574F
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
J
J
J
J
J
N
20
20
20
20
20
20
20
20
1
1
None
None
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
1
CD54HC574F3A
CD54HCT374F3A
CD54HCT574F
CD54HCT574F3A
CD74HC374E
1
1
1
1
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC374M
CD74HC374M96
CD74HC574E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
SOIC
SOIC
PDIP
SOIC
SOIC
PDIP
SOIC
SOIC
TSSOP
DW
DW
N
20
20
20
20
20
20
20
20
20
20
20
20
25
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC574M
DW
DW
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HC574M96
CD74HCT374E
CD74HCT374M
CD74HCT374M96
CD74HCT574E
CD74HCT574M
CD74HCT574M96
CD74HCT574PWR
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
DW
DW
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
DW
DW
PW
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
2000
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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相关型号：
CD54HCT377F/3A
IC HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20, FF/Latch
RENESAS
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