CD54HCT377F3A [TI]
High-Speed CMOS Logic Octal D-Type Flip-Flop With Data Enable; 高速CMOS逻辑八路D型触发器随着数据启用
| 型号： | CD54HCT377F3A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Octal D-Type Flip-Flop With Data Enable |
| 文件： | 总13页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC377, CD74HC377,
CD54HCT377, CD74HCT377
Data sheet acquired from Harris Semiconductor
SCHS184C
High-Speed CMOS Logic
Octal D-Type Flip-Flop With Data Enable
September 1997 - Revised February 2004
Features
Description
• Buffered Common Clock
• Buffered Inputs
The ’HC377 and ’HCT377 are octal D-type flip-flops with a
buffered clock (CP) common to all eight flip-flops. All the flip-
flops are loaded simultaneously on the positive edge of the
clock (CP) when the Data Enable (E) is Low.
[ /Title
(CD74
HC377
,
• Typical Propagation Delay at C = 15pF,
L
o
V
= 5V, T = 25 C
CC
A
Ordering Information
- 14 ns (HC Types
CD74
HCT37
7)
/Sub-
ject
(High
Speed
CMOS
Logic
Octal
D-
- 16 ns (HCT Types)
TEMP. RANGE
o
PART NUMBER
CD54HC377F3A
CD54HCT377F3A
CD74HC377E
( C)
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
• Fanout (Over Temperature Range)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
CD74HC377M
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
20 Ld TSSOP
20 Ld PDIP
• Significant Power Reduction Compared to LSTTL
Logic ICs
CD74HC377M96
CD74HC377PW
CD74HC377PWR
CD74HCT377E
CD74HCT377M
CD74HCT377M96
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30%of V
IL IH
at
Type
Flip-
CC
V
= 5V
CC
20 Ld SOIC
20 Ld SOIC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
NOTE: When ordering, use the entire part number. The suffixes
96 and R denote tape and reel.
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Pinout
CD54HC377, CD54HCT377
(CERDIP)
CD74HC377
(PDIP, SOIC, TSSOP)
CD74HCT377
(PDIP, SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
9
V
CC
E
20
19
Q
Q
0
0
1
1
2
2
3
3
7
7
6
D
D
Q
Q
D
D
Q
18 D
17 D
16 Q
15 Q
14 D
6
5
5
4
13 D
12
Q
4
GND 10
11 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Functional Diagram
3
4
2
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
5
7
6
8
9
13
14
17
18
12
15
16
19
11
1
CP
E
GND = 10
= 20
V
CC
TRUTH TABLE
INPUTS
OUPUTS
OPERATING MODE
CP
↑
E
l
D
Q
n
n
Load “1”
h
H
Load “0”
↑
l
l
L
Hold (Do Nothing)
↑
h
H
X
X
No Change
No Change
X
H = High Voltage Level Steady State.
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition.
L = Low Voltage Level Steady State.
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition.
X = Don’t Care.
↑ = Low to High Clock Transition.
Logic Diagram
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
E
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D Q
CP
CP
CP
CP
CP
CP
CP
CP
CP
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
2
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . .
69
58
83
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
DC Output Source or Sink Current per Output Pin, I
O
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
E
UNIT LOADS
1.5
0.5
CP
All D Inputs
0.25
n
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
Maximum Clock
Frequency
f
-
-
2
6
-
-
-
-
-
-
-
-
-
-
-
-
5
25
29
100
20
17
-
-
-
-
-
-
4
20
23
120
24
20
-
-
-
-
-
-
MHz
MHz
MHz
ns
MAX
4.5
6
30
35
80
16
14
Clock Pulse Width
t
2
W
4.5
6
ns
ns
4
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
Set-up Time,
SYMBOL CONDITIONS (V)
MIN
60
12
10
3
TYP
MAX
MIN
75
15
13
3
MAX
MIN
90
18
15
3
MAX
UNITS
ns
t
-
-
-
2
4.5
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SU
E, Data to CP
ns
ns
Hold Time,
Data to CP
t
t
2
ns
H
H
4.5
6
3
3
3
ns
3
3
3
ns
Hold Time,
E to CP
2
5
5
5
ns
4.5
6
5
5
5
ns
5
5
5
ns
HCT TYPES
Maximum Clock
Frequency
f
-
4.5
25
-
-
20
-
16
-
MHz
MAX
Clock Pulse Width
t
-
-
4.5
4.5
20
12
-
-
-
-
25
15
-
-
30
18
-
-
ns
ns
W
Set-up, Time
E, Data to CP
t
SU
Hold Time,
Data to CP
t
-
-
4.5
4.5
3
5
-
-
-
-
3
5
-
-
3
5
-
-
ns
ns
H
H
Hold Time,
E to CP
t
Switching Specifications Input t , t = 6ns
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
HC TYPES
MIN TYP MAX MIN
MAX
MIN
MAX UNITS
Propagation Delay (Figure 1)
CP to Q
t
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
175
35
-
-
-
-
-
-
-
-
-
-
-
220
44
-
-
-
-
-
-
-
-
-
-
-
265
53
-
ns
ns
PLH,
L
PHL
C =15pF
14
-
ns
L
C = 50pF
6
30
75
15
13
10
-
37
95
19
16
10
-
45
110
22
19
10
-
ns
L
Output Transition Time
(Figure 1)
t
, t
C = 50pF
2
-
ns
TLH THL
L
4.5
6
-
ns
-
ns
Input Capacitance
C
C = 50pF
-
-
pF
MHz
pF
IN
L
Maximum Clock Frequency
f
C =15pF
5
60
31
MAX
L
Power Dissipation Capacitance
(Notes 3, 4)
C
C =15pF
5
-
-
-
PD
L
HCT TYPES
Propagation Delay (Figure 1)
t
t
C = 50pF
4.5
5
-
-
-
-
16
-
38
-
-
-
-
48
-
-
-
-
57
-
ns
ns
ns
PLH,
L
PHL
CP to Q
C =15pF
L
Output Transition Time
(Figure 1)
t
, t
C = 50pF
4.5
15
19
22
TLH THL
L
Input Capacitance
C
C = 50pF
-
-
-
10
-
10
-
10
pF
IN
L
5
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
V
CC
(V)
PARAMETER
SYMBOL CONDITIONS
MIN TYP MAX MIN
MAX
MIN
MAX UNITS
Maximum Clock Frequency
f
C =15pF
5
5
-
-
50
35
-
-
-
-
-
-
-
-
-
-
MHz
pF
MAX
L
Power Dissipation Capacitance
(Notes 3, 4)
C
C =15pF
L
PD
NOTES:
3. C
is used to determine the dynamic power consumption, per flip-flop.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage.
D
CC
i
L
i
L
CC
Test Circuits and Waveforms
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
H(H)
t
t
H(L)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
PDIP
Drawing
5962-8976901RA
CD54HC377F3A
CD54HCT377F3A
CD74HC377E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
20
20
20
20
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
J
1
N
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC377EE4
CD74HC377M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
N
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
DW
DW
DW
DW
PW
PW
PW
PW
N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC377M96
CD74HC377M96E4
CD74HC377ME4
CD74HC377PW
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PDIP
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC377PWE4
CD74HC377PWR
CD74HC377PWRE4
CD74HCT377E
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HCT377EE4
CD74HCT377M
PDIP
N
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SOIC
DW
DW
DW
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT377M96
CD74HCT377M96E4
CD74HCT377ME4
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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Copyright 2005, Texas Instruments Incorporated
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