CD54HCT640 [TI]
High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting; 高速CMOS逻辑八路三态总线收发器，反相
| 型号： | CD54HCT640 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Octal Three-State Bus Transceiver, Inverting |
| 文件： | 总11页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC640, CD74HC640,
CD54HCT640, CD74HCT640
Data sheet acquired from Harris Semiconductor
SCHS192B
High-Speed CMOS Logic
Octal Three-State Bus Transceiver, Inverting
January 1998 - Revised May 2003
Features
Description
• Buffered Inputs
The ’HC640 and ’HCT640 silicon-gate CMOS three-state
bidirectional inverting and non-inverting buffers are intended
for two-way asynchronous communication between data
buses. They have high drive current outputs which enable
high-speed operation when driving large bus capacitances.
These circuits possess the low power dissipation of CMOS
• Three-State Outputs
[ /Title
(CD74
HC640
,
• Applications in Multiple-Data-Bus Architecture
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
circuits, and have speeds comparable to low power Schottky
CD74
HCT64
0)
/Sub-
ject
(High
Speed
CMOS
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads TTL circuits. They can drive 15 LSTTL loads. The ’HC640
and ’HCT640 are inverting buffers.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
The direction of data flow (A to B, B to A) is controlled by the
DIR input.
• Significant Power Reduction Compared to LSTTL
Logic ICs
Outputs are enabled by a low on the Output Enable input
(OE); a high OE puts these devices in the high impedance
mode.
• HC Types
- 2V to 6V Operation
Ordering Information
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
TEMP. RANGE
o
PART NUMBER
CD54HC640F3A
CD54HCT640F3A
CD74HC640E
( C)
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
• HCT Types
- 4.5V to 5.5V Operation
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
CD74HC640M
20 Ld SOIC
Pinout
CD74HCT640E
CD74HCT640M
20 Ld PDIP
CD54HC640, CD54HCT640
(CERDIP)
20 Ld SOIC
CD74HC640, CD74HCT640
(PDIP, SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
9
V
DIR
A0
A1
A2
A3
A4
A5
A6
A7
20
19
CC
OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12
B6
GND 10
11 B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
Functional Diagram
A0
B0
A1
THRU
A6
B1
THRU
B6
A7
B7
OE
OUTPUT ENABLE AND
V
= 20
CC
GND = 10
DIRECTION-SELECT LOGIC
DIR
TRUTH TABLE
CONTROL INPUTS DATA PORT STATUS
OE
L
DIR
L
A
B
n
n
O
I
H
H
Z
Z
I
Z
Z
O
H
L
L
H
To prevent excess currents in the High-Z modes all I/O terminals
should be terminated with 1kΩ to 1MΩ resistors.
H = High Level
L = Low Level
I = Input
O = Output (Inversion of Input Level)
Z = High Impedance
2
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
69
58
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-6
4.5
6
3.98
-
3.84
-
3.7
-
-7.8
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
6
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
7.8
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
Three-State Leakage
Current
I
V
or V
V
=
or
6
-
-
±0.5
-
±5
-
±10
µA
OZ
IL
IH
O
V
CC
GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-6
0.02
6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
5.5
5.5
5.5
-
-
-
-
-
-
±0.1
8
-
-
-
±1
80
±5
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
±10
CC
CC
GND
Three-State Leakage
Current
I
V
or V
V =
O
±0.5
OZ
IL
IH
V
or
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
DIR
0.9
1.5
1.5
OE, A
B
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
4
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
HC TYPES
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
t
, t
PHL PLH
C
= 50pF
L
A to B
B to A
2
-
-
-
90
18
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
115
23
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
135
27
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
7
-
L
L
L
6
-
15
150
30
-
20
190
38
-
23
225
45
-
Output High-Z
To High Level,
To Low Level
t
t
2
-
-
PHL, PLH
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
-
12
-
L
L
L
6
-
26
150
30
-
33
190
38
-
38
225
45
-
Output High Level
Output Low Level to High Z
t
t
2
-
-
PHZ, PLZ
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
-
12
-
L
L
L
6
-
26
60
12
10
10
20
33
75
15
13
10
20
38
90
18
15
10
20
Output Transition Time
Input Capacitance
t
, t
THL TLH
2
-
-
4.5
6
-
-
-
-
C
C
= 50pF
-
-
10
-
-
IN
L
Three-State Output
Capacitance
C
-
-
O
Power Dissipation Capacitance
(Notes 3, 4)
C
-
5
-
38
-
-
-
-
-
pF
PD
HCT TYPES
Propagation Delay
A to B
B to A
t
t
t
C
C
C
C
= 50pF
= 15pF
= 50pF
= 15pF
4.5
5
-
-
-
-
-
9
22
-
-
-
-
-
28
-
-
-
-
-
33
-
ns
ns
ns
ns
PHL, PLH
L
L
L
L
Output High-Z
To High Level,
To Low Level
t
4.5
5
-
30
-
38
-
45
-
PHL, PLH
12
Output High Level
Output Low Level to High Z
t
t
t
C
C
C
C
= 50pF
= 15pF
= 50pF
= 50pF
-
4.5
5
-
-
-
12
-
30
-
-
-
-
-
-
38
-
-
-
-
-
-
45
-
ns
ns
ns
pF
pF
PHZ, PLZ
L
L
L
L
Output Transition Time
Input Capacitance
, t
THL TLH
4.5
-
-
12
10
20
15
10
20
18
10
20
C
10
-
-
IN
Three-State Output
Capacitance
C
-
-
O
Power Dissipation Capacitance
(Notes 3, 4)
C
-
5
-
41
-
-
-
-
-
pF
PD
NOTES:
3. C
is used to determine the dynamic power consumption, per channel.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage.
D
CC
i
L
i
L
CC
5
CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 7. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 9. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 10. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 11. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
6
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
PDIP
Drawing
5962-8974001RA
CD54HC640F3A
CD54HCT640F3A
CD74HC640E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
20
20
20
20
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
J
1
N
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC640M
CD74HCT640E
CD74HCT640M
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
SOIC
DW
N
20
20
20
25
20
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
DW
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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