CD74AC10M96 [TI]
3 通道、3 输入、1.5V 至 5.5V 与非门 | D | 14 | -55 to 125;
| 型号： | CD74AC10M96 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3 通道、3 输入、1.5V 至 5.5V 与非门 | D | 14 | -55 to 125 栅 栅极 |
| 文件： | 总5页 (文件大小：32K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74AC10,
CD74ACT10
Data sheet acquired from Harris Semiconductor
SCHS227
September 1998
Triple 3-Input NAND Gate
Features
Description
• Typical Propagation Delay
o
The CD74AC10 and CD74ACT10 are triple 3-input NAND
gates that utilize the Harris Advanced CMOS Logic technology.
- 6ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
Ordering Information
PART
NUMBER
TEMP.
PKG.
NO.
o
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld PDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
CD74AC10E
CD74ACT10E
CD74AC10M
CD74ACT10M
NOTES:
E14.3
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
E14.3
[ /Title
(CD74
AC10,
CD74
ACT10
)
M14.15
M14.15
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
/Sub-
ject
- Drives 50Ω Transmission Lines
(Triple
3-Input
NAND
Gate)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Advan
ced
Pinout
Functional Diagram
CD74AC10, CD74ACT10
(PDIP, SOIC)
14
13
12
11
10
9
1
2
3
4
5
6
7
V
1A
1B
CC
TOP VIEW
1C
1Y
3C
3B
3A
3Y
2A
1A
1B
1
2
3
4
5
6
7
14 V
CC
13 1C
12 1Y
11 3C
10 3B
2B
2A
2C
2B
2C
2Y
2Y
9
8
3A
3Y
8
GND
GND
TRUTH TABLE
CMOS
,Harris
Semi-
con-
INPUTS
OUTPUTS
nA
L
nB
L
nC
L
nY
H
H
H
H
H
H
H
L
ductor,
Advan
ced
TTL)
/Cre-
ator ()
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
File Number 1977.1
1
CD74AC10, CD74ACT10
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
175
o
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
2
CD74AC10, CD74ACT10
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V) (mA)
I
(V)
1.5
3
MIN
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
±0.1
4
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±1
40
µA
µA
I
CC
GND
Quiescent Supply Current,
SSI
I
V
GND
or
0
80
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
-0.05
-24
4.5
4.5
5.5
5.5
4.5
4.5
5.5
4.4
-
4.4
-
-
4.4
-
V
V
V
V
V
V
V
OH
IH
IH
IL
IL
3.94
-
3.8
3.7
-
-
-75
-
-
-
-
-
-
-
3.85
-
-
-50
-
-
-
-
-
3.85
-
Low Level Output Voltage
V
or V
0.05
24
0.1
0.36
-
0.1
0.44
1.65
-
-
-
0.1
0.5
-
OL
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
80
3
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
0
-
±0.1
4
±1
40
2.8
µA
µA
mA
I
CC
GND
Quiescent Supply Current,
SSI
I
V
GND
or
CC
CC
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
V
4.5 to
5.5
2.4
CC
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
ACT Input Load Table
INPUT
UNIT LOAD
All
0.19
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
3
CD74AC10, CD74ACT10
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay, Input to
Output
t
, t
PLH PHL
1.5
3.3
-
-
-
139
-
-
-
153
ns
ns
4.4
15.5
4.3
17.1
(Note 9)
5
3.1
-
11.1
3.1
-
12.2
ns
(Note 10)
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
50
50
PD
(Note 11)
ACT TYPES
Propagation Delay, Input to
Output
t
5
3.5
-
12.3
3.4
-
13.5
ns
PHL
(Note 10)
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
50
50
PD
(Note 11)
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V.
11. C
is used to determine the dynamic power consumption per gate.
PD
AC: P = V
2
f (C
+ C )
D
CC
i
PD
L
2
ACT: P = V
f (C
+ C ) + V
∆I
where f = input frequency, C = output load capacitance, V
= supply voltage.
D
CC
i
PD
L
CC CC
i
L
CC
t = 3ns
f
t = 3ns
r
OUTPUT
INPUT
LEVEL
R
(NOTE)
500Ω
90%
V
S
L
V
I
DUT
10%
GND
V
OUTPUT
LOAD
C
L
50pF
O
V
S
NOTE: For AC Series Only: When V
Input Level
= 1.5V, R = 1kΩ.
L
CC
t
t
PLH
PHL
CD74AC
CD74ACT
V
3V
FIGURE 2. PROPAGATION DELAY TIMES
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 1. PROPAGATION DELAY TIMES
4
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1999, Texas Instruments Incorporated
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