CD74AC139MG4 [TI]
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS;
| 型号： | CD74AC139MG4 |
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TEXAS INSTRUMENTS |
| 描述： | DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS 驱动 光电二极管 逻辑集成电路 |
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CD74AC139,
CD74ACT139
Data sheet acquired from Harris Semiconductor
SCHS235
September 1998
Dual 2-to-4-Line Decoder/Demultiplexer
Features
Description
• Buffered Inputs
The CD74AC139 and CD74ACT139 are dual 2-to-4-line
decoders/demultiplexers that utilize the Harris Advanced
CMOS Logic technology. These devices contain two inde-
pendent binary to one-of-four decoders, each with a single
active LOW enable input (1E or 2E). Data on the select
inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four
normally HIGH outputs to go LOW.
• Typical Propagation Delay
o
- 5.4ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
If the enable input is HIGH, all four outputs remain HIGH. For
demultiplexer operation, the enable input is the data input.
The enable input also functions as a chip select when these
devices are cascaded.
[ /Title
(CD74
AC139
,
CD74
ACT13
9)
/Sub-
ject
(Dual
2-to-4-
Line
Decod
er/Dem
ulti-
plexer)
/Autho
r ()
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
Ordering Information
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
PART
NUMBER
TEMP.
RANGE ( C)
PKG.
NO.
o
PACKAGE
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
o
CD74AC139E
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
E16.3
- Drives 50Ω Transmission Lines
o
CD74ACT139E
0 to 70 C, -40 to 85, 16 Ld PDIP
E16.3
-55 to 125
o
CD74AC139M96 0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
M16.15
M16.15
o
CD74ACT139M
0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
/Key-
words
(Har-
ris
Semi-
con-
Pinout
CD74AC139, CD74ACT139
(PDIP, SOIC)
TOP VIEW
ductor,
Advan
ced
CMOS
)
/Cre-
ator ()
/DOCI
NFO
1E
1A0
1A1
1Y0
1Y1
1Y2
1Y3
GND
1
2
3
4
5
6
7
8
16 V
CC
15 2E
14 2A0
13 2A1
12 2Y0
11 2Y1
10 2Y2
9
2Y3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
File Number 1953.1
1
CD74AC139, CD74ACT139
Functional Diagram
4
5
6
7
2
1A0
1Y0
1Y1
1Y2
1Y3
DECODER
1
3
1
1A1
1E
12
11
10
9
14
2A0
2Y0
2Y1
2Y2
2Y3
DECODER
2
13
15
2A1
2E
GND = 8
= 16
V
CC
TRUTH TABLE
INPUTS
ENABLE
SELECT
OUTPUTS
E
A1
A0
L
Y3
H
H
H
L
Y2
H
H
L
Y1
H
L
Y0
L
L
L
L
L
H
L
H
H
H
H
L
H
H
X
H
H
H
L
H
X
H
H
H
H
X = Don’t Care
2
CD74AC139, CD74ACT139
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD74AC139, CD74ACT139
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
±0.1
8
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±1
80
µA
µA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
0
160
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
0
-
±0.1
8
±1
80
2.8
µA
µA
mA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
160
3
CC
CC
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
V
4.5 to
5.5
2.4
CC
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
ACT Input Load Table
INPUT
A0, A1
E
UNIT LOAD
1
0.67
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
4
CD74AC139, CD74ACT139
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay, A0, A1 to
Outputs
t
, t
PLH PHL
1.5
3.3
-
-
-
119
-
-
-
131
ns
ns
3.9
13.4
3.7
14.7
(Note 9)
5
2.8
-
9.5
2.6
-
10.5
ns
(Note 10)
Propagation Delay,
E to Outputs
t
, t
PLH PHL
1.5
3.1
5
-
3.9
2.8
-
-
-
119
13.4
9.5
10
-
3.7
2.6
-
-
-
131
14.7
10.5
10
ns
ns
ns
pF
pF
-
-
Input Capacitance
C
-
-
-
I
Power Dissipation Capacitance
C
-
-
83
-
-
83
-
PD
(Note 11)
ACT TYPES
Propagation Delay, A0, A1 to
Outputs
t
, t
PLH PHL
5
3.1
3.2
-
-
10.5
10.9
2.9
3
-
-
11.5
12
ns
ns
(Note 10)
Propagation Delay,
E to Outputs
t
, t
PLH PHL
5
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
83
83
PD
(Note 11)
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V.
11. C
is used to determine the dynamic power consumption per decoder/demultiplexer.
PD
AC: P = V
2
f (C
+ C )
D
CC
i
PD
L
2
ACT: P = V
f (C
PD
+ C ) + V
∆I
where f = input frequency, C = output load capacitance, V
= supply voltage.
CC
D
CC
i
L
CC CC
i
L
3ns
3ns
INPUT
LEVEL
90%
V
S
A1
t = 3ns
r
t = 3ns
f
10%
INPUT
LEVEL
GND
90%
V
INPUT E
S
t
PHL
t
PLH
10%
GND
t
t
PHL
PLH
INPUT Y3
V
S
OUTPUT Y3
V
S
FIGURE 2.
FIGURE 1.
5
CD74AC139, CD74ACT139
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
NOTE: For AC Series Only: When V
Input Level
= 1.5V, R = 1kΩ.
CC
L
CD74AC
CD74ACT
3V
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 3. PROPAGATION DELAY TIMES
6
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