CD74AC164 [TI]
8-Bit Serial-In/Parallel-Out Shift Register; 8位串行输入/并行输出移位寄存器
| 型号： | CD74AC164 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Bit Serial-In/Parallel-Out Shift Register |
| 文件： | 总8页 (文件大小：39K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54/74AC164,
CD54/74ACT164
Data sheet acquired from Harris Semiconductor
SCHS240A
8-Bit Serial-In/Parallel-Out Shift Register
September 1998 - Revised May 2000
Features
Description
[ /Title
(CD74
AC164
,
CD74
ACT16
4)
/Sub-
ject (8-
Bit
Serial-
In/Par-
allel-
Out
Shift
Regis-
ter)
/Autho
r ()
/Key-
words
(Har-
ris
• Buffered Inputs
The ’AC164 and ’ACT164 are 8-bit serial-in/parallel-out shift
registers with asynchronous reset that utilize Advanced
CMOS Logic technology. Data is shifted on the positive edge
of the clock (CP). A LOW on the Master Reset (MR) pin
resets the shift register and all outputs go to the LOW state
regardless of the input conditions. Two Serial Data inputs
(DS1 and DS2) are provided; either one can be used as a
Data Enable control.
• Typical Propagation Delay
o
- 6ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
Ordering Information
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
NUMBER
TEMP.
o
RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
14 Ld PDIP
• Balanced Propagation Delays
CD54AC164F3A
CD74AC164E
CD74AC164M
CD54ACT164F3A
CD74ACT164E
CD74ACT164M
NOTES:
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
14 Ld SOIC
14 Ld CERDIP
14 Ld PDIP
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
14 Ld SOIC
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
Semi-
con-
ductor,
Advan
ced
Pinout
CD54AC164, CD54ACT164
(CERDIP)
CD74AC164, CD74ACT164
(PDIP, SOIC)
CMOS
,Harris
Semi-
con-
ductor,
Advan
ced
TTL)
/Cre-
ator ()
TOP VIEW
DS1
DS2
Q0
1
2
3
4
5
6
7
14 V
CC
13 Q7
12 Q6
11 Q5
10 Q4
Q1
Q2
Q3
9
8
MR
CP
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
1
Copyright © 2000, Texas Instruments Incorporated
CD54/74AC164, CD54/74ACT164
Functional Diagram
3
1
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DS1
DS2
4
5
6
10
11
12
13
9
8
MR
CP
GND = 7
= 14
V
CC
MODE SELECT - TRUTH TABLE
INPUTS
OUTPUTS
Q1 - Q7
OPERATING MODE
RESET (CLEAR)
SHIFT
MR
L
CP
X
↑
DS1
DS2
Q0
L
X
l
X
l
L - L
H
L
q0 - q6
q0 - q6
q0 - q6
q0 - q6
H
↑
l
h
l
L
H
↑
h
h
L
H
↑
h
H
H = HIGH voltage level steady state.
L = LOW voltage level steady state.
h = HIGH voltage level one setup time prior to the LOW-to_HIGH clock transition.
= LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.
X = Don’t care.
l
q = Lowercase letters indicate the state of the referenced output prior to the LOW-to-HIGH clock transition.
↑ = LOW-to-HIGH clock transition.
2
CD54/74AC164, CD54/74ACT164
I
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
175
o
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD54/74AC164, CD54/74ACT164
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
±0.1
8
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±1
80
µA
µA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
0
160
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
0
-
±0.1
8
±1
80
2.8
µA
µA
mA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
160
3
CC
CC
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
4.5 to
5.5
2.4
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
ACT Input Load Table
INPUT
DS1, DS2
MR
UNIT LOAD
0.5
0.74
CP
0.71
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
4
CD54/74AC164, CD54/74ACT164
Prerequisite For Switching Function
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
UNITS
CC
AC TYPES
Max. Clock Frequency
f
1.5
3.3
7
-
-
6
-
-
MHz
MHz
MAX
62
54
(Note 9)
5
86
-
75
-
MHz
(Note 10)
MR Pulse Width
CP Pulse Width
Set-up Time
t
t
1.5
3.3
5
49
5.5
3.9
73
8.2
5.9
27
3.1
2.2
27
3.1
2.2
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
56
6.3
4.5
84
9.4
6.7
31
3.5
2.5
31
3.5
2.5
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W
1.5
3.3
5
W
t
1.5
3.3
5
SU
Hold Time
t
1.5
3.3
5
H
MR to CP Removal Time
t
1.5
3.3
5
REM
1
1
1
1
ACT TYPES
Max. Clock Frequency
f
5
80
-
70
-
MHz
MAX
(Note 10)
MR Pulse Width
CP Pulse Width
Set-up Time
t
t
5
5
5
5
5
3.9
6.2
2.2
2.6
0
-
-
-
-
-
4.5
7.1
2.5
3
-
-
-
-
-
ns
ns
ns
ns
ns
W
W
t
SU
Hold Time
t
H
MR to CP Removal Time
t
0
REM
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay,
CP to Qn
t
, t
1.5
3.3
-
-
-
143
-
-
-
157
ns
ns
PLH PHL
4.5
15.9
4.4
17.5
(Note 9)
5
3.2
-
11.4
3.1
-
12.5
ns
(Note 10)
5
CD54/74AC164, CD54/74ACT164
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Propagation Delay,
SYMBOL
, t
V
(V)
MIN
TYP
MAX
158
17.7
12.6
10
MIN
TYP
MAX
UNITS
ns
CC
t
1.5
3.3
5
-
5
-
-
4.9
3.5
-
-
174
19.5
13.9
10
PLH PHL
MR to Qn
-
-
ns
3.6
-
-
-
-
-
ns
Input Capacitance
C
-
pF
I
Power Dissipation Capacitance
C
-
-
150
-
-
150
-
pF
PD
(Note 11)
ACT TYPES
Propagation Delay, CP to Qn
t , t
PLH PHL
5
3.8
-
13.5
3.7
-
14.9
ns
(Note 10)
Propagation Delay, MR to Qn
Input Capacitance
t
, t
PLH PHL
5
-
4.1
-
-
14.4
10
-
4
-
-
-
15.8
10
-
ns
pF
pF
C
-
-
I
Power Dissipation Capacitance
C
-
150
-
150
PD
(Note 11)
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V.
11. C
P
is used to determine the dynamic power consumption per device.
PD
= C
2
2
V
f Σ (C V
f ) + V
o
∆I , where f = input frequency, f = output frequency, C = output load capacitance, V
=
CC
D
PD CC
i
L
CC
CC CC
i
o
L
supply voltage.
t
r
t
f
t
w
INPUT
GND
90%
INPUT LEVEL
GND
CP
V
S
V
10%
MR
S
t
w
t
PHL
1/f
MAX
ANY
INPUT
t
t
V
PLH
PHL
S
ANY
OUTPUT
90%
10%
t
V
REC
S
INPUT LEVEL
GND
t
t
CP
V
S
TLH
THL
FIGURE 1.
FIGURE 2.
VALID
INPUT
LEVEL
V
S
DS2 (1)
GND
t
t
H
INPUT
LEVEL
SU
INPUT LEVEL
GND
V
DS1 (2)
CP
DS2 (1)
S
V
S
GND
t
t
H
SU
t
t
SU
REC
t
H
INPUT
LEVEL
INPUT LEVEL
GND
V
V
CP
S
S
GND
FIGURE 3.
FIGURE 4.
6
CD54/74AC164, CD54/74ACT164
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
NOTE: For AC Series Only: When V
= 1.5V, R = 1kΩ.
CC
L
AC
ACT
3V
Input Level
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 5. PROPAGATION DELAY TIMES
7
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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