CD74AC175M96G4 [TI]
具有复位功能的四路 D 型触发器 | D | 16 | -55 to 125;
| 型号： | CD74AC175M96G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有复位功能的四路 D 型触发器 | D | 16 | -55 to 125 光电二极管 逻辑集成电路 触发器 锁存器 |
| 文件： | 总7页 (文件大小：37K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74AC175,
CD74ACT175
Data sheet acquired from Harris Semiconductor
SCHS242
September 1998
Quad D Flip-Flop with Reset
Features
Description
[ /Title
(CD74
AC175
,
CD74
ACT17
5
• Buffered Inputs
The CD74AC175 and CD74ACT175 are quad D flip-flops
with reset that utilize the Harris Advanced CMOS Logic tech-
nology. Information at the D input is transferred to the Q and
Q outputs on the positive-going edge of the clock pulse. All
four flip-flops are controlled by a common clock (CP) and a
common reset (MR). Resetting is accomplished by a LOW
logic level independent of the clock.
• Typical Propagation Delay
o
- 6.4ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
)
Ordering Information
/Sub-
ject
(Quad
D Flip-
Flop
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
NUMBER
TEMP.
PKG.
NO.
o
RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
• Balanced Propagation Delays
CD74AC175E
CD74ACT175E
CD74AC175M
CD74ACT175M
NOTES:
E16.3
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
E16.3
M16.15
M16.15
with
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
Reset)
/Autho
r ()
/Key-
words
(Har-
ris
- Drives 50Ω Transmission Lines
13. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
14. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
Semi-
con-
Pinout
CD74AC175, CD74ACT175
(PDIP, SOIC)
TOP VIEW
ductor,
Advan
ced
CMOS
,Harris
Semi-
con-
ductor,
Advan
ced
MR
Q0
1
2
3
4
5
6
7
8
16 V
CC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
Q0
D0
D1
Q1
Q1
9
CP
GND
TTL)
/Cre-
ator ()
/DOCI
NFO
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © Harris Corporation 1998
File Number 1964.1
1
CD74AC175, CD74ACT175
Functional Diagram
4
2
D0
D
Q
Q0
Q0
9
CP
CP
R
3
1
Q
MR
5
7
6
D1
D
Q
Q
Q1
Q1
CP
R
12
10
11
D2
D
Q
Q
Q2
Q2
CP
R
13
15
14
D3
D
Q
Q
Q3
Q3
CP
R
GND = 8
V
= 16
CC
TRUTH TABLE (EACH FLIP-FLOP)
INPUTS
OUTPUTS
RESET
(MR)
CLOCK
CP
DATA
Dn
Qn
Qn
H
L
H
H
H
X
↑
X
H
L
L
H
L
↑
L
H
L
X
Q0
Q0
H
L
X
↑
= High Level (Steady State)
= Low Level (Steady State)
= Irrelevant
= Transition from Low to High level
Q0, Q0 = Level before the Indicated Steady-State Input conditions
were established.
2
CD74AC175, CD74ACT175
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
15. For up to 4 outputs per device, add ±25mA for each additional output.
16. Unless otherwise specified, all voltages are referenced to ground.
17. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD74AC175, CD74ACT175
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
±0.1
8
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±1
80
µA
µA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
0
160
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
0
-
±0.1
8
±1
80
2.8
µA
µA
mA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
160
3
CC
CC
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
V
4.5 to
5.5
2.4
CC
CC
-2.1
NOTES:
18. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
19. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
ACT Input Load Table
INPUT
Dn
UNIT LOAD
0.58
MR
0.67
CP
0.92
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
4
CD74AC175, CD74ACT175
Prerequisite For Switching Function
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
UNITS
CC
AC TYPES
Data to CP Set-Up Time
t
1.5
3.3
2
2
-
-
2
2
-
-
ns
ns
SU
(Note 8)
5
2
-
2
-
ns
(Note 9)
Hold Time
t
1.5
3.3
5
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
H
2
2
ns
Removal Time, MR to CP
MR Pulse Width
CP Pulse Width
CP Frequency
t
REM
1.5
3.3
5
1
1
ns
1
1
ns
1
1
ns
t
1.5
3.3
5
44
4.9
3.5
55
6.1
4.4
9
50
5.6
4
ns
W
W
ns
ns
t
1.5
3.3
5
63
7
ns
ns
5
ns
f
MAX
1.5
3.3
5
8
MHz
MHz
MHz
81
114
71
100
ACT TYPES
Data to CP Set-Up Time
t
5
2
-
2
-
ns
SU
(Note 9)
Hold Time
t
5
5
5
5
5
2
1
-
-
-
-
-
2
1
-
-
-
-
-
ns
ns
H
Removal Time, MR to CP
MR Pulse Width
Clock Pulse Width
CP Frequency
t
f
REM
t
3.5
4.4
114
4
ns
W
W
t
5
ns
114
MHz
MAX
NOTES:
20. 3.3V Min is at 3V.
21. 5V Min is at 4.5V.
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
Propagation Delay, CP to Q, Q
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
t
, t
1.5
3.3
-
-
-
139
-
-
-
153
ns
ns
PLH PHL
4.4
15.5
4.3
17.1
(Note 11)
5
3.2
-
11.1
3.1
-
12.2
ns
(Note 12)
5
CD74AC175, CD74ACT175
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
, t
V
(V)
MIN
TYP
MAX
139
15.5
11.1
10
MIN
TYP
MAX
UNITS
ns
CC
Propagation Delay, MR to Q, Q
t
1.5
3.3
5
-
4.4
3.2
-
-
-
-
4.3
3.1
-
-
-
153
17.1
12.2
10
PLH PHL
ns
-
-
ns
Input Capacitance
C
-
-
-
pF
I
Power Dissipation Capacitance
C
-
-
55
-
-
55
-
pF
PD
(Note 13)
ACT TYPES
Propagation Delay, CP to Qn
t
, t
PLH PHL
5
3
-
10.5
2.9
-
11.5
ns
(Note 12)
Propagation Delay, MR to Qn
Input Capacitance
t
, t
PLH PHL
5
-
3.3
-
-
11.8
10
-
3.3
-
-
13
10
-
ns
pF
pF
C
-
-
-
-
I
Power Dissipation Capacitance
C
-
55
55
PD
(Note 13)
NOTES:
22. Limits tested 100%.
23. 3.3V Min is at 3.6V, Max is at 3V.
24. 5V Min is at 5.5V, Max is at 4.5V.
25. C is used to determine the dynamic power consumption per flip-flop.
PD
2
P
= C
V
f + Σ (C + V 2 f ) + V
∆I
where f = input frequency, f = output frequency, C = output load capacitance, V
=
D
PD CC
i
L
CC
o
CC CC
i
o
L
CC
supply voltage.
INPUT LEVEL
V
MR
V
S
S
GND
t
t
REM
W
INPUT
INPUT LEVEL
CP
CP
V
V
V
V
S
S
S
S
GND
t
W
t
t
PHL
t
PLH
PHL
Q
Q
V
V
V
S
S
S
FIGURE 5. PROPAGATION DELAYS
FIGURE 6. RESET OR SET PREREQUISITE AND
PROPAGATION DELAYS
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
INPUT LEVEL
GND
D
V
V
V
V
S
S
S
S
t (H)
H
t (L)
NOTE: For AC Series Only: When V
Input Level
= 1.5V, R = 1kΩ.
CC L
H
t
(H)
SU
t
(L)
SU
INPUT LEVEL
CP
CD74AC
CD74ACT
3V
V
V
S
S
GND
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 7.
FIGURE 8. PROPAGATION DELAY TIMES
6
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1999, Texas Instruments Incorporated
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