CD74AC273 [TI]
Octal D Flip-Flop with Reset; 八路D触发器与复位
| 型号： | CD74AC273 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal D Flip-Flop with Reset |
| 文件： | 总8页 (文件大小：39K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54AC273, CD74AC273
CD54ACT273, CD74ACT273
Data sheet acquired from Harris Semiconductor
SCHS249A
August 1998 - Revised April 2000
Octal D Flip-Flop with Reset
Features
Description
• Buffered Inputs
The ’AC273 and ’ACT273 devices are octal D-type flip-flops
with reset that utilize advanced CMOS logic technology.
Information at the D input is transferred to the Q output on
the positive-going edge of the clock pulse. All eight flip-flops
are controlled by a common clock (CP) and a common reset
• Typical Propagation Delay
o
- 6.5ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
(MR). Resetting is accomplished by a low voltage level
independent of the clock.
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
Ordering Information
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
NUMBER
TEMPERATURE
RANGE
PACKAGE
20 Ld PDIP
20 Ld CDIP
20 Ld PDIP
20 Ld CDIP
20 Ld SOIC
20 Ld SOIC
• Balanced Propagation Delays
o
o
CD74AC273E
CD54AC273F3A
CD74ACT273E
CD54ACT273F3A
CD74AC273M
CD74ACT273M
NOTES:
-40 C to 85 C
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
o
o
-55 C to 125 C
o
o
-40 C to 85 C
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
o
o
-55 C to 125 C
o
o
-40 C to 85 C
- Drives 50Ω Transmission Lines
o
o
-40 C to 85 C
Pinout
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
CD54AC273, CD54ACT273
(CDIP)
CD74AC273, CD74ACT273
(PDIP, SOIC)
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office for
ordering information.
TOP VIEW
1
2
3
4
5
6
7
8
9
V
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
20
19
CC
Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12
Q4
GND 10
11 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
1
Copyright © 2000, Texas Instruments Incorporated
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
Functional Diagram
CLOCK
CP
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DATA
INPUTS
DATA
OUTPUTS
D4
D5
D6
D7
RESET MR
TRUTH TABLE
INPUTS
OUTPUTS
RESET
(MR)
CLOCK
CP
DATA
Dn
Qn
L
L
H
H
H
X
↑
X
H
L
H
↑
L
L
X
Q0
H = High level (steady state), L = Low level (steady state), X = Irrel-
evant, ↑ = Transition from Low to High level, Q0 = The level of Q
before the indicated steady-state input conditions were estab-
lished.
2
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
Thermal Resistance, θ (Typical, Note 5)
JA
CC
DC Input Diode Current, I
For V < -0.5V or V > V
o
IK
E Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 C/W
M Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 C/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
Temperature Range, T
CD54AC273, CD54ACT273 . . . . . . . . . . . . . . . . . -55 C to 125 C
CD74AC273, CD74ACT273 . . . . . . . . . . . . . . . . . . -40 C to 85 C
Supply Voltage Range, V (Note 4)
A
o
o
o
o
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
CC
I
O
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. The package thermal impedance is calculated in accordance with JESD 51.
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
±0.1
8
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±1
80
µA
µA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
0
160
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
0
-
±0.1
8
±1
80
2.8
µA
µA
mA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
160
3
CC
CC
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
4.5 to
5.5
2.4
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
ACT Input Load Table
INPUT
Dn
UNIT LOAD
0.5
0.57
1
MR
CP
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
4
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
Prerequisite For Switching Function
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
UNITS
CC
AC TYPES
Data to CP Set-Up Time
t
1.5
3.3
2
2
-
-
2
2
-
-
ns
ns
SU
(Note 9)
5
2
-
2
-
ns
(Note 10)
Hold Time
t
1.5
3.3
5
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
H
2
2
ns
Removal Time, MR to CP
MR Pulse Width
CP Pulse Width
CP Frequency
t
REM
1.5
3.3
5
2
2
ns
2
2
ns
2
2
ns
t
1.5
3.3
5
55
6.1
4.4
55
6.1
4.4
9
63
7
ns
W
W
ns
5
ns
t
1.5
3.3
5
63
7
ns
ns
5
ns
f
MAX
1.5
3.3
5
8
MHz
MHz
MHz
81
114
71
100
ACT TYPES
Data to CP Set-Up Time
t
5
2
-
2
-
ns
SU
(Note 10)
Hold Time
t
5
5
5
5
5
2
-
-
-
-
-
2
2
-
-
-
-
-
ns
ns
H
Removal Time MR to CP
MR Pulse Width
CP Pulse Width
CP Frequency
t
f
2
REM
t
4.4
5.3
97
5
ns
W
W
t
6
ns
85
MHz
MAX
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay,
CP to Qn
t
, t
1.5
3.3
-
-
-
154
-
-
-
169
ns
ns
PLH PHL
4.9
17.2
4.7
18.9
(Note 9)
5
3.5
-
12.3
3.4
-
13.5
ns
(Note 10)
5
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Propagation Delay,
SYMBOL
, t
V
(V)
MIN
TYP
MAX
154
17.2
12.3
10
MIN
TYP
MAX
UNITS
ns
CC
t
1.5
3.3
5
-
4.9
3.5
-
-
-
-
4.7
3.4
-
-
-
169
18.9
13.5
10
PLH PHL
MR to Qn
ns
-
-
ns
Input Capacitance
C
-
-
-
pF
I
Power Dissipation Capacitance
C
-
-
45
-
-
45
-
pF
PD
(Note 11)
ACT TYPES
Propagation Delay,
CP to Qn
t
, t
PLH PHL
5
3.5
3.5
-
-
12.3
12.3
3.4
3.4
-
-
13.5
13.5
ns
ns
(Note 10)
Propagation Delay,
MR to Qn
t , t
PLH PHL
5
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
45
45
PD
(Note 11)
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. C
is used to determine the dynamic power consumption per flip-flop.
PD
AC: P = C
2
2
V
f = ∑ (C
V
f )
D
PD CC
i
L
CC
o
2
2
ACT: P = C
V
f + ∑ (C
V
f ) + V
∆I
where f = input frequency, f = output frequency, C = output load capacitance,
D
PD CC
i
L
CC
o
CC CC
i
o
L
V
= supply voltage.
CC
INPUT
LEVEL
INPUT
LEVEL
t
r
t
MR
f
V
V
S
S
GND
90%
S
V
S
CP
10%
V
V
S
t
10%
REM
t
W
INPUT
t
CP
(Q)
W
t
V
PLH
S
t
PHL
t
PLH
V
V
S
Q
S
Q
V
S
FIGURE 1. PROPAGATION DELAY TIMES AND CLOCK
PULSE WIDTH
FIGURE 2. PREREQUISITE AND PROPAGATION DELAY
TIMES FOR MASTER RESET
6
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273
OUTPUT
LEVEL
D
V
V
V
t
V
S
S
t
S
t
S
(L)
t (H)
H
H
(L)
(H)
SU
SU
CP
V
V
S
S
FIGURE 3. PREREQUISITE FOR CLOCK
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
NOTE: For AC Series Only: When V
= 1.5V, R = 1kΩ.
CC
L
AC
ACT
3V
Input Level
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 4. PROPAGATION DELAY TIMES
7
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 2000, Texas Instruments Incorporated
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