CD74AC283 [TI]
4-Bit Binary Fill Adder With Fast Carry; 4位二进制填写的加法器，快进
| 型号： | CD74AC283 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-Bit Binary Fill Adder With Fast Carry |
| 文件： | 总5页 (文件大小：32K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54/74AC283,
CD54/74ACT283
Data sheet acquired from Harris Semiconductor
SCHS251D
4-Bit Binary Fill Adder With Fast Carry
August 1998 - Revised May 2000
Features
Description
• Buffered Inputs
The ’AC283 and ’ACT283 4-bit binary adders with fast carry
that utilize Advanced CMOS Logic technology. These
devices add two 4-bit binary numbers and generate a carry-
out bit if the sum exceeds 15.
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
Because of the symmetry of the add function, this device
can be used with either all active-HIGH operands (positive
logic) or with all active-LOW operands (negative logic).
When using positive logic, the carry-in input must be tied
LOW if there is no carry-in.
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
Ordering Information
PART
NUMBER
TEMP.
RANGE ( C)
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
o
PACKAGE
CD54AC283F3A
CD74AC283E
-55 to 125
o
16 Ld CERDIP
- Drives 50Ω Transmission Lines
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
o
CD74AC283M
0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
CD54ACT283F3A
CD74ACT283E
-55 to 125
o
16 Ld CERDIP
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
o
CD74ACT283M
NOTES:
0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office or
customer service for ordering information.
Pinout
Functional Diagram
CD54AC283, CD54ACT283
(CERDIP)
CD74AC283, CD74ACT283
(PDIP, SOIC)
5
4
A0
B0
A1
B1
A2
B2
A3
B3
S0
S1
S2
S3
C
6
3
1
TOP VIEW
S1
B1
A1
S0
A0
B0
1
2
3
4
5
6
7
8
16 V
CC
2
15 B2
14 A2
13 S2
12 A3
11 B3
10 S3
14
15
12
13
10
9
11
7
C
IN
GND = 8
= 16
V
CC
C
9
C
OUT
GND
IN
OUT
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright © 2000, Texas Instruments Incorporated
1
CD54/74AC283, CD54/74ACT283
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
Thermal Impedance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
JA
o
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 C/W
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 C/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
o
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. The package thermal impedance is calculated in accordance with JESD 51.
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
2
CD54/74AC283, CD54/74ACT283
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
±0.1
8
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±1
80
µA
µA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
0
160
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
0
-
±0.1
8
±1
80
2.8
µA
µA
mA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
160
3
CC
CC
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
4.5 to
5.5
2.4
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
ACT Input Load Table
INPUT
A0, B0, A2, B2
A1, B1
UNIT LOAD
1.66
1.9
1.4
1.1
A3, B3
C
IN
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
3
CD54/74AC283, CD54/74ACT283
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
Propagation Delay,
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
t , t
PLH PHL
1.5
3.3
-
-
-
199
-
-
-
219
ns
ns
An or Bn to C
OUT
6.3
22.4
6.2
24.6
C
C
to Sn
to C
OUT
IN
IN
(Note 9)
5
4.5
-
16
4.4
-
17.6
ns
(Note 10)
Propagation Delay,
An or Bn to Sn
t
, t
PLH PHL
1.5
3.3
5
-
6.6
4.7
-
-
207
23.2
16.5
10
-
6.4
4.6
-
-
228
25.5
18.2
10
ns
ns
ns
pF
pF
-
-
-
-
-
-
Input Capacitance
C
-
I
Power Dissipation Capacitance
C
-
-
120
-
-
120
-
PD
(Note 11)
ACT TYPES
Propagation Delay,
t
, t
PLH PHL
5
4.5
-
-
16
2.7
-
-
17.6
ns
An or Bn to C
(Note 10)
OUT
C
C
to Sn
to C
OUT
IN
IN
Propagation Delay,
An or Bn to Sn
t , t
PLH PHL
5
4.7
16.5
3.3
18.2
ns
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
120
120
PD
(Note 11)
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. C
is used to determine the dynamic power consumption per function.
PD
AC: P = V
2
f (C
+ C )
D
CC
i
PD
L
2
ACT: P = V
f (C
PD
+ C ) + V
∆I
CC CC
where f = input frequency, C = output load capacitance, V
= supply voltage.
CC
D
CC
i
L
i
L
OUTPUT
t ≤ 3ns
t ≤ 3ns
f
r
INPUT LEVEL
90%
R
(NOTE)
L
500Ω
DUT
V
S
INPUT
10%
OUTPUT
LOAD
C
L
50pF
GND
NOTE: For AC Series Only: When V
= 1.5V, R = 1kΩ.
CC
L
AC
ACT
3V
INVERTING
OUTPUT
V
S
Input Level
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
t
t
PLH
PHL
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 2. PROPAGATION DELAY TIMES
FIGURE 1. PROPAGATION DELAY TIMES
4
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Copyright 2000, Texas Instruments Incorporated
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