CD74ACT139M96E4 [TI]
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS; 双路2号线至4线解码器/多路解复用器型号: | CD74ACT139M96E4 |
厂家: | TEXAS INSTRUMENTS |
描述: | DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS |
文件: | 总10页 (文件大小:319K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD54ACT139, CD74ACT139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCHS337 – MARCH 2003
CD54ACT139 . . . F PACKAGE
CD74ACT139 . . . E OR M PACKAGE
(TOP VIEW)
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
Buffered Inputs
1G
1A
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
2G
2A
2B
Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception
1B
1Y0
1Y1
1Y2
1Y3
GND
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
12 2Y0
11
10
9
2Y1
2Y2
2Y3
Balanced Propagation Delays
±24-mA Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The ’ACT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V V
CC
operation. These devices are designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. In high-performance memory systems, these
decoders can be used to minimize the effects of system decoding. When used with high-speed memories
utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are
less than the typical access time of the memory. This means that the effective system delay introduced by the
decoders is negligible.
The active-low enable (G) input can be used as a data line in demultiplexing applications. These
decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its
driving circuit.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – E
SOIC – M
CDIP – F
Tube
Tube
CD74ACT139E
CD74ACT139M
CD74ACT139E
–55°C to 125°C
ACT139M
Tape and reel CD74ACT139M96
Tube CD54ACT139F3A
CD54ACT139F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT139, CD74ACT139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCHS337 – MARCH 2003
FUNCTION TABLE
(each decoder/demultiplexer)
INPUTS
OUTPUTS
SELECT
G
B
X
L
A
X
L
Y0
H
L
Y1
H
H
L
Y2
H
H
H
L
Y3
H
H
H
H
L
H
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
logic diagram (positive logic)
4
1Y0
1Y1
1Y2
1
1G
5
6
2
1A
Select
Inputs
7
3
1Y3
1B
Data
Outputs
12
2Y0
2Y1
2Y2
15
2G
11
10
14
2A
Select
Inputs
9
13
2Y3
2B
†
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
JA
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT139, CD74ACT139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCHS337 – MARCH 2003
recommended operating conditions (see Note 3)
–55°C to
125°C
–40°C to
85°C
T
A
= 25°C
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
0.8
V
0
0
V
V
0
0
V
V
0
0
V
V
V
I
CC
CC
CC
Output voltage
V
O
CC
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
–24
24
–24
24
–24
24
mA
mA
ns/V
OH
OL
∆t/∆v
10
10
10
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
–55°C to
125°C
–40°C to
85°C
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
I
I
I
I
= –50 µA
= –24 mA
= –50 mA
= –75 mA
= 50 µA
4.5 V
4.5 V
5.5 V
5.5 V
4.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
OH
OH
OH
OH
OL
OL
OL
OL
3.94
3.7
3.8
V
V
V = V or V
IH
V
OH
I
IL
†
†
3.85
3.85
0.1
0.1
0.5
0.1
= 24 mA
0.36
0.44
V = V or V
V
OL
I
IH
IL
†
= 50 mA
= 75 mA
1.65
†
1.65
±1
I
I
V = V
or GND
or GND,
±0.1
±1
µA
µA
I
I
CC
CC
V = V
I
I
O
= 0
8
160
80
CC
‡
V = V
I
– 2.1 V
4.5 V to 5.5 V
2.4
10
3
2.8
10
mA
pF
I
CC
CC
C
10
i
†
‡
Testoneoutputatatime, notexceeding1-secondduration. Measurementismadebyforcingindicatedcurrentandmeasuringvoltagetominimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load
ACT INPUT LOAD TABLE
INPUT
A or B
G
UNIT LOAD
1
0.67
Unit Load is ∆I
electrical characteristics table
limit specified in
CC
(e.g., 2.4 mA at 25°C).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT139, CD74ACT139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCHS337 – MARCH 2003
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V, C = 50 pF (unless otherwise noted) (see Figure 1)
CC
L
–55°C to
125°C
–40°C to
85°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
2.9
2.9
3
MAX
MIN
3.1
3.1
3.2
3.2
MAX
t
t
t
t
11.5
11.5
12
10.5
10.5
10.9
10.9
PLH
PHL
PLH
PHL
A or B
G
Y
Y
ns
ns
3
12
operating characteristics, T = 25°C
A
PARAMETER
TYP
UNIT
C
Power dissipation capacitance
83
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT139, CD74ACT139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SCHS337 – MARCH 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
t
t
/t
Open
R1 = 500 Ω
R2 = 500 Ω
PLH PHL
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
/t
PHZ PZH
C
= 50 pF
L
(see Note A)
t
w
3 V
0 V
1.5 V
1.5 V
Input
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
Reference
Input
3 V
0 V
1.5 V
CLR
Input
1.5 V
0 V
t
t
h
su
t
rec
3 V
0 V
Data
Input
90%
t
90%
3 V
0 V
1.5 V
10%
1.5 V
10%
1.5 V
CLK
t
r
f
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3 V
0 V
3 V
Input
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
Output
Waveform 1
In-Phase
Output
90%
t
≈V
CC
50%
10%
50% V
10%
CC
V
20% V
20% V
CC
S1 at 2 × V
(see Note B)
CC
OL
CC
t
f
r
V
OL
t
t
PLH
PHL
90%
t
t
PHZ
PZH
V
V
OH
90%
Output
Waveform 2
S1 at GND
Out-of-Phase
Output
50% V
10%
50%
10%
CC
V
OH
80% V
80% V
CC
CC
OL
t
t
r
f
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
Phase relationships between waveforms are arbitrary.
D. For clock inputs, f is measured with the input duty cycle at 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
pd
PLH
PZL
PLZ
PHL
PZH
PHZ
are the same as t
are the same as t
.
en
dis
.
I. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
PDIP
Drawing
CD54ACT139F3A
CD74ACT139E
ACTIVE
ACTIVE
J
16
16
1
TBD
A42 SNPB
N / A for Pkg Type
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74ACT139EE4
CD74ACT139M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
N
D
D
D
D
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74ACT139M96
CD74ACT139M96E4
CD74ACT139ME4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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