CD74ACT163ME4 [TI]
4-BIT SYNCHRONOUS BINARY COUNTERS; 4位同步二进制计数器
| 型号： | CD74ACT163ME4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-BIT SYNCHRONOUS BINARY COUNTERS |
| 文件： | 总18页 (文件大小：677K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54ACT163, CD74ACT163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS300B – APRIL 2000 – REVISED MARCH 2003
CD54ACT163 . . . F PACKAGE
CD74ACT163 . . . E OR M PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
CLR
CLK
A
V
CC
RCO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Synchronously Programmable
Q
A
B
Q
B
description/ordering information
C
Q
C
The ’ACT163 devices are 4-bit binary counters.
These synchronous, presettable counters feature
an internal carry look-ahead for application in
high-speed counting designs. Synchronous
operation is provided by having all flip-flops
D
Q
D
ENP
GND
ENT
LOAD
clocked simultaneously so that the outputs change, coincident with each other, when instructed by the
count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting
spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of the clock waveform.
The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low
after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000
(LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15, with Q high). This high-level overflow ripple-carry pulse
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – E
Tube
Tube
CD74ACT163E
CD74ACT163M
CD74ACT163M96
CD54ACT163F3A
CD74ACT163E
–55°C to 125°C
SOIC – M
CDIP – F
ACT163M
Tape and reel
Tube
CD54ACT163F3A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT163, CD74ACT163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS300B – APRIL 2000 – REVISED MARCH 2003
FUNCTION TABLE
INPUTS
OUTPUTS
Q RCO
n
FUNCTION
Reset (clear)
Parallel load
CLR
CLK
ENP
ENT
LOAD
A,B,C,D
L
h
h
h
h
h
↑
↑
X
X
X
h
l
X
X
X
h
X
l
X
l
X
l
L
L
L
L
H
↑
l
h
X
X
X
Note 1
↑
h
h
h
Count
Note 1 Count
X
X
q
q
Note 1
Inhibit
L
n
X
n
H = high level, L = low level, X = don’t care, h = high level one setup time prior to the CLK
low-to-high transition, l = low level one setup time prior to the CLK low-to-high transition, q = the
state of the referenced output prior to the CLK low-to-high transition, and ↑ = CLK low-to-high
transition.
NOTE 1: The RCO output is high when ENT is high and the counter is at terminal count
(HHHH).
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT163, CD74ACT163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS300B – APRIL 2000 – REVISED MARCH 2003
logic diagram (positive logic)
9
LOAD
10
ENT
15
RCO
†
LD
7
ENP
†
CK
2
CLK
1
CK
LD
CLR
R
M1
G2
1, 2T/1C3
14
13
Q
Q
A
B
G4
3D
4R
3
A
M1
G2
1, 2T/1C3
G4
3D
4R
4
B
M1
G2
1, 2T/1C3
12
Q
C
G4
3D
4R
5
C
M1
G2
1, 2T/1C3
11
Q
D
G4
3D
4R
6
D
†
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT163, CD74ACT163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS300B – APRIL 2000 – REVISED MARCH 2003
logic symbol, each D/T flip-flop
LD (Load)
M1
G2
1, 2T/1C3
TE (Toggle Enable)
CK (Clock)
Q (Output)
G4
3D
4R
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
†
TG
TG
LD
TG
Q
TG
†
LD
†
CK
D
R
†
CK
TG
TG
†
†
CK
CK
†
The origins of LD and CK are shown in the logic diagram of the overall device.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT163, CD74ACT163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS300B – APRIL 2000 – REVISED MARCH 2003
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (synchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT163, CD74ACT163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS300B – APRIL 2000 – REVISED MARCH 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
JA
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
–55°C to
125°C
–40°C to
85°C
T
A
= 25°C
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
MIN
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
4.5
2
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
0.8
V
0
0
V
V
0
0
V
V
0
0
V
V
V
I
CC
CC
CC
Output voltage
V
O
CC
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
–24
24
–24
24
–24
24
mA
mA
ns
OH
OL
∆t/∆v
10
10
10
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT163, CD74ACT163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS300B – APRIL 2000 – REVISED MARCH 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
–55°C to
125°C
–40°C to
85°C
T
A
= 25°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
4.4
3.94
–
MAX
MIN
4.4
3.7
3.85
–
MAX
MIN
4.4
3.8
–
MAX
I
I
I
I
I
I
I
I
= –50 µA
= –24 mA
= –50 mA
= –75 mA
= 50 µA
4.5 V
4.5 V
5.5 V
5.5 V
4.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
OH
OH
OH
OH
OL
OL
OL
OL
V
V
V = V or V
IH
V
OH
I
IL
†
†
–
3.85
0.1
0.36
–
0.1
0.5
1.65
–
0.1
0.44
–
= 24 mA
V = V or V
V
OL
I
IH
IL
†
= 50 mA
= 75 mA
†
–
1.65
±1
I
I
V = V
or GND
or GND,
±0.1
8
±1
µA
µA
I
I
CC
CC
V = V
I
I
O
= 0
160
80
CC
4.5 V to
5.5 V
‡
V = V
I
–2.1 V
2.4
3
2.8
mA
I
CC
CC
C
10
10
10
pF
i
†
‡
Testoneoutputatatime, notexceeding1-secondduration. Measurementismadebyforcingindicatedcurrentandmeasuringvoltagetominimize
power dissipation. Test verifies a minimum 50- transmission-line drive capability at 85°C and 75- transmission-line drive capability at 125°C.
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load
ACT INPUT LOAD TABLE
INPUT
A, B, C, or D
UNIT LOAD
0.13
1
CLK
CLR, ENT
LOAD
ENP
0.83
0.67
0.5
Unit Load is ∆I
characteristics table (e.g., 2.4 mA at 25°C).
limit specified in electrical
CC
timing requirements over recommended operating conditions (unless otherwise noted)
–55°C to
125°C
–40°C to
85°C
UNIT
MIN
MAX
80
MIN
MAX
91
f
t
Clock frequency
Pulse duration
MHz
ns
clock
CLK high or low
A, B, C, or D
ENP or ENT
LOAD low
6.2
5
5.4
4.4
5.3
6.6
6.6
0
w
6
t
Setup time, before CLK↑
Hold time, after CLK↑
ns
ns
su
h
7.5
7.5
0
CLR inactive
A, B, C, or D
ENP or ENT
LOAD low
0
0
t
0
0
CLR inactive
0
0
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT163, CD74ACT163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS300B – APRIL 2000 – REVISED MARCH 2003
switching characteristics over recommended operating conditions, C = 50 pF (unless otherwise
L
noted) (see Figure 1)
–55°C to
125°C
–40°C to
85°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
80
MAX
MIN
91
MAX
f
MHz
max
pd
RCO
Any Q
RCO
4.2
4.1
2.7
16.7
16.5
10.8
4.3
4.2
2.8
15.2
15
CLK
ENT
t
ns
9.8
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
66
pF
pd
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD54ACT163, CD74ACT163
4-BIT SYNCHRONOUS BINARY COUNTERS
SCHS300B – APRIL 2000 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
S1
R1 = 500 Ω
R2 = 500 Ω
t
/t
Open
PLH PHL
From Output
Under Test
t
/t
2 × V
CC
GND
PLZ PZL
t
/t
PHZ PZH
C
= 50 pF
L
(see Note A)
t
w
3 V
0 V
NOTE: When V
= 1.5 V, R1 and R2 = 1 kΩ.
CC
Input
1.5 V
1.5 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
0 V
3 V
Reference
Input
CLR
Input
1.5 V
1.5 V
0 V
t
t
h
su
t
rec
3 V
0 V
3 V
0 V
Data
Input
90%
90%
1.5 V
1.5 V
10%
1.5 V
10%
CLK
t
t
r
f
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
Output
Control
1.5 V
1.5 V
t
t
PLH
PHL
90%
t
t
PZL
PLZ
V
OH
In-Phase
Output
Output
Waveform 1
90%
t
≈V
CC
50%
10%
50% V
10%
CC
V
50% V
CC
CC
V
+ 0.3 V
OL
S1 at 2 × V
(see Note B)
OL
CC
t
f
r
V
OL
t
t
PLH
PHL
90%
t
t
PZH
PHZ
V
V
OH
Output
Waveform 2
S1 at Open
(see Note B)
90%
Out-of-Phase
Output
V
50% V
10%
50%
10%
OH
CC
V
– 0.3 V
≈0 V
OH
50% V
OL
t
t
f
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
Phase relationships between waveforms are arbitrary.
D. For clock inputs, f is measured with the input duty cycle at 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
pd
PLH
PZL
PLZ
PHL
PZH
PHZ
are the same as t
are the same as t
.
en
dis
.
I. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
PDIP
Drawing
CD54ACT163F3A
CD74ACT163E
ACTIVE
ACTIVE
J
16
16
1
TBD
A42 SNPB
N / A for Pkg Type
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74ACT163EE4
CD74ACT163M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
N
D
D
D
D
D
D
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74ACT163M96
CD74ACT163M96E4
CD74ACT163M96G4
CD74ACT163ME4
CD74ACT163MG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CD74ACT163M96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 16
SPQ
Length (mm) Width (mm) Height (mm)
333.2 345.9 28.6
CD74ACT163M96
D
2500
Pack Materials-Page 2
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