CD74ACT174M96G4 [TI]
HEX D-TYPE FLIP-FLOPS WITH CLEAR;
| 型号： | CD74ACT174M96G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HEX D-TYPE FLIP-FLOPS WITH CLEAR |
| 文件： | 总7页 (文件大小：38K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74AC174,
CD54/74ACT174
Data sheet acquired from Harris Semiconductor
SCHS241A
Hex D Flip-Flop with Reset
September 1998 - Revised May 2000
Features
Description
[ /Title
(CD74
AC174
,
CD74
ACT17
4
• Buffered Inputs
The CD74AC174 and ’ACT174 are hex D flip-flops with reset
that utilize Advanced CMOS Logic technology. Information at
the D input is transferred to the Q output on the positive-
going edge of the clock pulse. All six flip-flops are controlled
by a common clock (CP) and a common reset (MR). Reset-
ting is accomplished by a low voltage level independent of
the clock.
• Typical Propagation Delay
o
- 6.4ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
)
Ordering Information
/Sub-
ject
(HexD
Flip-
Flop
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
PART
NUMBER
TEMP.
o
RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld PDIP
16 Ld SOIC
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
• Balanced Propagation Delays
CD74AC174E
CD74AC174M
CD54ACT174F3A
CD74ACT174E
CD74ACT174M
NOTES:
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
with
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
Reset)
/Autho
r ()
- Drives 50Ω Transmission Lines
/Key-
words
(Har-
ris
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
Semi-
con-
Pinout
ductor,
Advan
ced
CD54ACT174
(CERDIP)
CD74AC174, CD74ACT174
(PDIP, SOIC)
CMOS
,Harris
Semi-
con-
ductor,
Advan
ced
TTL)
/Cre-
ator ()
/DOCI
NFO
TOP VIEW
MR
Q0
1
2
3
4
5
6
7
8
16 V
CC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
D0
D1
Q1
D2
Q2
9
CP
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
1
Copyright © 2000, Texas Instruments Incorporated
CD74AC174, CD54/74ACT174
Functional Diagram
9
CP
3
D0
CP
D
2
Q0
R
4
5
D1
Q1
7
6
Q2
D2
11
10
Q3
D3
13
12
D4
Q4
14
15
D5
Q5
1
MR
GND = 8
V
= 16
CC
TRUTH TABLE (EACH FLIP-FLOP)
INPUTS
OUTPUTS
RESET
(MR)
CLOCK
CP
DATA
Dn
Qn
L
L
H
H
H
X
↑
X
H
L
H
↑
L
L
X
Q0
H = High Level (Steady State)
L
X
↑
= Low Level (Steady State)
= Irrelevant
= Transition from Low to High level
Q0 = Level before the Indicated Steady-State Input conditions
were established.
2
CD74AC174, CD54/74ACT174
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . . 1505 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD74AC174, CD54/74ACT174
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
±0.1
8
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±1
80
µA
µA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
0
160
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
0
-
±0.1
8
±1
80
2.8
µA
µA
mA
I
CC
GND
Quiescent Supply Current
MSI
I
V
GND
or
160
3
CC
CC
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
4.5 to
5.5
2.4
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
ACT Input Load Table
INPUT
Dn, MR
CP
UNIT LOAD
0.5
0.83
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
4
CD74AC174, CD54/74ACT174
Prerequisite For Switching Function
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
UNITS
CC
AC TYPES
Data to CP Set-Up Time
t
1.5
3.3
2
2
-
-
2
2
-
-
ns
ns
SU
(Note 9)
5
2
-
2
-
ns
(Note 10)
Hold Time
t
1.5
3.3
5
33
3.7
2.6
1.5
1.5
1.5
44
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
38
4.2
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
H
ns
Removal Time, MR to CP
MR Pulse Width
CP Pulse Width
CP Frequency
t
REM
1.5
3.3
5
1.5
1.5
1.5
50
5.6
4
ns
ns
ns
t
1.5
3.3
5
ns
W
W
4.9
3.5
57
ns
ns
t
1.5
3.3
5
65
7.3
5.2
8
ns
6.4
4.6
9
ns
ns
f
MAX
1.5
3.3
5
MHz
MHz
MHz
77
68
95
108
ACT TYPES
Data to CP Set-Up Time
t
5
2
-
2
-
ns
SU
(Note 10)
Hold Time
t
5
5
5
5
5
2.2
1.5
3.5
5.4
91
-
-
-
-
-
2.5
1.5
4
-
-
-
-
-
ns
ns
H
Removal Time, MR to CP
MR Pulse Width
Clock Pulse Width
CP Frequency
t
f
REM
t
ns
W
W
t
6.2
80
ns
MHz
MAX
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
Propagation Delay, CP to Qn
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
t
, t
1.5
3.3
-
-
-
154
-
-
-
169
ns
ns
PLH PHL
4.9
17.2
4.7
18.9
(Note 9)
5
3.5
-
12.3
3.4
-
13.5
ns
(Note 10)
5
CD74AC174, CD54/74ACT174
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case) (Continued)
r
f
L
o
o
o
o
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
, t
V
(V)
MIN
TYP
MAX
165
18.5
13.2
10
MIN
TYP
MAX
UNITS
ns
CC
Propagation Delay, MR to Qn
t
1.5
3.3
5
-
5.2
3.7
-
-
-
-
5.1
3.6
-
-
-
181
20.3
14.5
10
PLH PHL
ns
-
-
ns
Input Capacitance
C
-
-
-
pF
I
Power Dissipation Capacitance
C
-
-
37
-
-
37
-
pF
PD
(Note 11)
ACT TYPES
Propagation Delay, CP to Qn
t , t
PLH PHL
5
3.6
-
12.6
3.5
-
14
ns
(Note 10)
Propagation Delay, MR to Qn
Input Capacitance
t
, t
PLH PHL
5
-
4
-
-
-
14.1
10
-
3.9
-
-
15.5
10
-
ns
pF
pF
C
-
-
I
Power Dissipation Capacitance
C
-
-
37
37
PD
(Note 11)
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. C is used to determine the dynamic power consumption per flip-flop.
PD
2
P
= C
V
f + Σ (C + V 2 f ) + V
∆I
where f = input frequency, f = output frequency, C = output load capacitance, V
=
D
PD CC
i
L
CC
o
CC CC
i
o
L
CC
supply voltage.
INPUT LEVEL
GND
INPUT LEVEL
D
CP
V
V
V
V
S
S
S
S
V
V
V
S
S
S
GND
t (H)
H
t
t (L)
W
H
t
t
PLH
PHL
t
(H)
SU
t
(L)
SU
INPUT LEVEL
CP
V
V
S
V
V
S
S
S
GND
FIGURE 1. PROPAGATION DELAYS
FIGURE 3.
OUTPUT
INPUT LEVEL
R
(NOTE)
500Ω
V
L
MR
V
S
S
GND
DUT
t
t
REM
W
INPUT
CP
OUTPUT
LOAD
C
L
50pF
V
S
t
PHL
(Q)
NOTE: For AC Series Only: When V
= 1.5V, R = 1kΩ.
Q
CC
L
V
S
AC
ACT
3V
Input Level
V
CC
FIGURE 2. RESET OR SET PREREQUISITE AND
PROPAGATION DELAYS
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 4. PROPAGATION DELAY TIMES
6
IMPORTANT NOTICE
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subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 2000, Texas Instruments Incorporated
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