概述
规格参数
数据手册
替代型号CD74ACT253E 概述
Dual 4-Input Multiplexer, Three-State 双路4输入多路复用器，三态 逻辑控制器 复用器/解复用器
CD74ACT253E 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Active |
| 零件包装代码： | DIP | 包装说明： | DIP, DIP16,.3 |
| 针数： | 16 | Reach Compliance Code： | compliant |
| HTS代码： | 8542.39.00.01 | 风险等级： | 1.85 |
| Is Samacsys： | N | 系列： | ACT |
| JESD-30 代码： | R-PDIP-T16 | JESD-609代码： | e4 |
| 长度： | 19.3 mm | 负载电容（CL）： | 50 pF |
| 逻辑集成电路类型： | MULTIPLEXER | 最大I（ol）： | 0.024 A |
| 位数： | 4 | 功能数量： | 2 |
| 输入次数： | 4 | 输出次数： | 1 |
| 端子数量： | 16 | 最高工作温度： | 125 °C |
| 最低工作温度： | -55 °C | 输出特性： | 3-STATE |
| 输出极性： | TRUE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | DIP | 封装等效代码： | DIP16,.3 |
| 封装形状： | RECTANGULAR | 封装形式： | IN-LINE |
| 包装方法： | TUBE | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 5 V | 最大电源电流（ICC）： | 0.08 mA |
| Prop。Delay @ Nom-Sup： | 20 ns | 传播延迟（tpd）： | 18 ns |
| 认证状态： | Not Qualified | 座面最大高度： | 5.08 mm |
| 子类别： | Multiplexer/Demultiplexers | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 4.5 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | NO | 技术： | CMOS |
| 温度等级： | MILITARY | 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) |
| 端子形式： | THROUGH-HOLE | 端子节距： | 2.54 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 6.35 mm | Base Number Matches： | 1 |
CD74ACT253E 数据手册
通过下载CD74ACT253E数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载CD74AC253,
CD54/74ACT253
Data sheet acquired from Harris Semiconductor
SCHS247A
August 1998 - Revised May 2000
Dual 4-Input Multiplexer, Three-State
Features
Description
• Buffered Inputs
The CD74AC253 and ’ACT253 dual 4-input multiplexers that
utilize Advanced CMOS Logic technology. One of the four
sources for each section is selected by the common Select
inputs, S0 and S1. When the Output Enable (1OE or 2OE) is
HIGH, the output is in the high-impedance state.
• Typical Propagation Delay
o
- 6.3ns at V
= 5V, T = 25 C, C = 50pF
A L
CC
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
Ordering Information
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
PART
TEMP.
o
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
NUMBER
RANGE ( C)
PACKAGE
o
CD74AC253E
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
• Balanced Propagation Delays
o
CD74AC253M
0 to 70 C, -40 to 85, 16 Ld SOIC
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
-55 to 125
CD54ACT253F3A
CD74ACT253E
-55 to 125
o
16 Ld CERDIP
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
0 to 70 C, -40 to 85, 16 Ld PDIP
-55 to 125
- Drives 50Ω Transmission Lines
o
CD74ACT253M
NOTES:
0 to 70 C, -40 to 85, 16 Ld SOIC
-55 to 125
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
Pinout
CD54ACT253
(CERDIP)
CD74AC253, CD74ACT253
(PDIP, SOIC)
TOP VIEW
1OE
1
2
3
4
5
6
7
8
16 V
CC
15 2OE
14 S
S
1I
1I
1I
1I
1
3
2
1
0
0
13 2I
12 2I
11 2I
10 2I
3
2
1
0
1Y
9
2Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
1
Copyright © 2000, Texas Instruments Incorporated.
CD74AC253, CD54/74ACT253
Functional Diagram
1
1OE
6
1I
1I
1I
1I
0
1
2
3
5
4
3
7
1Y
SEL/MUX
14
2
S0
S1
10
11
12
13
15
2I
2I
2I
2I
0
1
2
3
9
SEL/MUX
2Y
GND = 8
= 16
V
CC
2OE
TRUTH TABLE
DATA INPUTS
ENABLE
INPUTS
SELECT INPUTS
OUTPUT
S1
X
L
S0
X
L
nI
nI
nI
nI
3
nOE
H
L
nY
Z
0
1
2
X
L
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
L
L
L
H
X
X
X
X
X
X
L
H
L
L
H
H
L
L
L
H
X
X
X
X
L
H
L
H
H
H
H
L
L
H
X
X
L
H
L
H
H
L
H
L
H
Select inputs S1 and S0 are common to both sections. H = High level, L = Low inputs, X = Don’t care, Z = High imped-
ance.
2
CD74AC253, CD54/74ACT253
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
Thermal Resistance (Typical, Note 5)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
___
___
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . 150C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
O
O
CC
DC V
or Ground Current, I
I
(Note 3) . . . . . . . . .±100mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
(Note 4)
CC
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
25 C
o
o
85 C
125 C
V
CC
PARAMETER
AC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
MAX
MIN
MAX
MIN
MAX UNITS
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
-
-
-
1.5
3
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
1.2
2.1
3.85
-
-
V
V
V
V
V
V
V
V
V
V
V
V
IH
-
-
-
5.5
1.5
3
-
-
-
V
-
0.3
0.3
0.3
IL
-
0.9
-
0.9
-
0.9
5.5
1.5
3
-
1.65
-
1.65
-
1.65
V
V
or V
IH IL
-0.05
1.4
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
1.4
2.9
4.4
2.48
3.8
3.85
-
-
-
-
-
-
1.4
2.9
4.4
2.4
3.7
-
-
-
-
-
-
-
OH
-0.05
-0.05
-4
4.5
3
-24
4.5
5.5
-75
(Note 6, 7)
-50
5.5
-
-
-
-
3.85
-
V
(Note 6, 7)
3
CD74AC253, CD54/74ACT253
DC Electrical Specifications (Continued)
o
o
TEST
CONDITIONS
-40 C TO
-55 C TO
o
o
o
25 C
MIN
85 C
125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
1.5
3
MAX
0.1
0.1
0.1
0.36
0.36
-
MIN
MAX
MIN
MAX UNITS
I
O
Low Level Output Voltage
V
V
or V
IH IL
0.05
0.05
0.05
12
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
0.1
0.5
0.5
-
V
V
V
V
V
V
OL
4.5
3
0.1
0.44
0.44
1.65
24
4.5
5.5
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±0.1
±0.5
±1
±5
µA
µA
I
CC
GND
Three-State Leakage
Current
I
V
V
or V
-
±10
OZ
IH
IL
= V
O
CC
or GND
Quiescent Supply Current
MSI
I
V
GND
or
0
5.5
-
8
-
80
-
160
µA
CC
CC
ACT TYPES
High Level Input Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input Voltage
High Level Output Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
V
V
V
or V
IH IL
-0.05
-24
4.5
4.5
5.5
4.4
3.94
-
-
-
-
4.4
3.8
-
-
-
4.4
3.7
-
-
-
-
V
V
V
OH
-75
(Note 6, 7)
3.85
-50
(Note 6, 7)
5.5
-
-
-
-
3.85
-
V
Low Level Output Voltage
V
or V
IH IL
0.05
24
4.5
4.5
5.5
-
-
-
0.1
0.36
-
-
-
-
0.1
-
-
-
0.1
0.5
-
V
V
V
OL
0.44
1.65
75
(Note 6, 7)
50
5.5
5.5
5.5
-
-
-
-
-
-
-
-
-
-
-
1.65
±1
V
(Note 6, 7)
Input Leakage Current
I
V
or
-
±0.1
±0.5
±1
±5
µA
µA
I
CC
GND
Three-State or Leakage
Current
I
V
V
or V
-
±10
OZ
IH
IL
= V
O
CC
or GND
Quiescent Supply Current
MSI
I
V
or
0
-
5.5
-
-
8
-
-
80
-
-
160
3
µA
CC
CC
GND
Additional Supply Current per
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
4.5 to
5.5
2.4
2.8
mA
CC
-2.1
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
o
o
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 C, 75Ω at 125 C.
4
CD74AC253, CD54/74ACT253
ACT Input Load Table
INPUT
UNIT LOAD
S0, S1, nI , nI
0
1
1
nOE
0.83
NOTE: Unit load is ∆I limit specified in DC Electrical Specifications
CC
o
Table, e.g., 2.4mA max at 25 C.
Switching Specifications Input t , t = 3ns, C = 50pF (Worst Case)
r
f
L
o
o
o
o
-40 C TO 85 C
TYP
-55 C TO 125 C
PARAMETER
AC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
TYP
MAX
UNITS
CC
Propagation Delay,
S0, S1, to Y
t , t
PLH PHL
1.5
3.3
-
-
-
227
25
-
-
-
250
28
ns
ns
7.2
7
(Note 9)
5
5.2
-
18.2
5
-
20
ns
(Note 10)
Propagation Delay,
nI to Y
t
, t
PLH PHL
1.5
3.3
5
-
4.8
3.4
-
-
-
-
-
-
-
-
151
16.9
12.1
131
15.7
10.5
15
-
-
-
-
-
-
-
-
166
18.6
13.3
144
17.3
11.5
15
ns
ns
ns
ns
ns
ns
pF
4.7
3.3
-
Propagation Delay,
Output Enable,
Output Disable to Y
t
, t
,
1.5
3.3
5
PLZ PHZ
t
, t
PZL PZH
4.5
3
4.3
2.9
-
Three-State Output
Capacitance
C
-
-
O
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
107
107
PD
(Note 11)
ACT TYPES
Propagation Delay,
S0, S1, to Y
t
, t
5
5.7
4.6
3.2
-
-
-
20
5.5
4.5
3.2
-
-
-
22
18
ns
ns
ns
PLH PHL
(Note 10)
Propagation Delay,
nI to Y
t
, t
5
5
16.4
11.5
PLH PHL
Propagation Delay,
Output Enable,
t
, t
,
12.6
PLZ PHZ
t
, t
PZL PZH
Output Disable to Y
Three-State Output
Capacitance
C
-
-
-
15
-
-
15
pF
O
Input Capacitance
C
-
-
-
-
-
10
-
-
-
-
10
-
pF
pF
I
Power Dissipation Capacitance
C
107
107
PD
(Note 11)
NOTES:
8. Limits tested 100%.
9. 3.3V Min is at 3.6V, Max is at 3V.
10. 5V Min is at 5.5V, Max is at 4.5V.
11. C
is used to determine the dynamic power consumption per multiplexer.
PD
AC: P = V
2
f (C
+ C )
D
CC
i
PD
L
2
ACT: P = V
f (C
PD
+ C ) + V
∆I
CC CC
where f = input frequency, C = output load capacitance, V
= supply voltage.
CC
D
CC
i
L
i
L
5
CD74AC253, CD54/74ACT253
t = 3ns
t = 3ns
f
r
INPUT LEVEL
90%
OUTPUT
DISABLE
V
S
10%
GND
t
t
t
t
PZL
PLZ
V
0.2V
OUTPUT: LOW
TO OFF TO LOW
S
CC
V
(≠ GND)
OL
PHZ
PZH
V
(≠ V
)
CC
OH
0.8 V
V
OUTPUT: HIGH
TO OFF TO HIGH
CC
S
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
GND (t
t
)
PHZ, PZH
OPEN (t
t
)
PHL, PLH
2 V
(t )
t
OTHER
CC PLZ, PZL
500Ω†
L
DUT
WITH
THREE-
STATE
OUTPUT
INPUTS
(TIED HIGH
OR LOW)
(OPEN DRAIN)
R
OUT
500Ω†
C
L
R
50pF
L
OUTPUT
DISABLE
†FOR AC SERIES ONLY: WHEN V
CC
= 1.5V, R = 1kΩ
L
FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT
t = 3ns
r
t = 3ns
f
INPUT
LEVEL
90%
V
S
10%
I OR S
V
S
OUTPUT Y
t
t
PHL
PLH
FIGURE 2. PROPAGATION DELAY TIMES
OUTPUT
R
(NOTE)
L
500Ω
DUT
OUTPUT
LOAD
C
L
50pF
NOTE: For AC Series Only: When V
= 1.5V, R = 1kΩ.
CC
L
AC
ACT
3V
Input Level
V
CC
Input Switching Voltage, V
0.5 V
0.5 V
1.5V
S
CC
CC
Output Switching Voltage, V
0.5 V
CC
S
FIGURE 3. PROPAGATION DELAY TIMES
6
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
CD74ACT253E CAD模型
引脚图
封装焊盘图
CD74ACT253E 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| CD74ACT253EE4 | TI | Dual 4-Input Multiplexer, Three-State | 完全替代 |
|
CD74ACT253E 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CD74ACT253EE4 | TI | Dual 4-Input Multiplexer, Three-State | 获取价格 |
|
| CD74ACT253EN | ETC | Logic IC | 获取价格 |
|
| CD74ACT253EX | RENESAS | Multiplexer, ACT Series, 2-Func, 4 Line Input, 1 Line Output, True Output, CMOS, PDIP16 | 获取价格 |
|
| CD74ACT253F | ETC | Logic IC | 获取价格 |
|
| CD74ACT253M | TI | Dual 4-Input Multiplexer, Three-State | 获取价格 |
|
| CD74ACT253M | RENESAS | IC,LOGIC MUX,DUAL,4-INPUT,ACT-CMOS,SOP,16PIN,PLASTIC | 获取价格 |
|
| CD74ACT253M | ROCHESTER | Multiplexer, ACT Series, 2-Func, 4 Line Input, 1 Line Output, True Output, CMOS, PDSO16 | 获取价格 |
|
| CD74ACT253M | GE | Multiplexer, ACT Series, 2-Func, 4 Line Input, 1 Line Output, True Output, CMOS, PDSO16, | 获取价格 |
|
| CD74ACT253M96 | TI | Dual 4-Input Multiplexer, Three-State | 获取价格 |
|
| CD74ACT253M96 | RENESAS | IC,LOGIC MUX,DUAL,4-INPUT,ACT-CMOS,SOP,16PIN,PLASTIC | 获取价格 |
|
CD74ACT253E 相关文章
HARTING(浩亭)圆形连接器产品选型手册
- 2024-10-31
- 6
HYCON(宏康科技)产品选型手册
- 2024-10-31
- 6
GREEGOO整流二极管和晶闸管产品选型手册
- 2024-10-31
- 7
西门子豪掷106亿美元，战略收购工程软件巨头Altair
- 2024-10-31
- 8
