CD74FCT245 [TI]
BiCMOS FCT Interface Logic, Octal-Bus Tranceivers, Three-State; 的BiCMOS FCT接口逻辑，八路总线Tranceivers ，三态
| 型号： | CD74FCT245 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BiCMOS FCT Interface Logic, Octal-Bus Tranceivers, Three-State |
| 文件： | 总7页 (文件大小：42K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54FCT245,
CD74FCT245
Data sheet acquired from Harris Semiconductor
SCHS271A
BiCMOS FCT Interface Logic,
January 1997 - Revised October 1999
Octal-Bus Tranceivers, Three-State
Features
Description
• Buffered Inputs
The CD54/74FCT245 octal bus transceiver uses a small
geometry BiCMOS technology. The output stage is a combi-
nation of bipolar and CMOS transistors that limits the output
• Typical Propagation Delay: 5.0ns at V
o
= 5V,
CC
T = 25 C
A
HIGH level to two diode drops below V . This resultant
CC
• Noninverting
lowering of output swing (0V to 3.7V) reduces power bus
• SCR Latchup Resistant BiCMOS Process and
Circuit Design
ringing (a source of EMI) and minimizes V
bounce and
CC
ground bounce and their effects during simultaneous output
switching. The output configuration also enhances switching
speed and is capable of sinking 48mA to 64mA.
• Speed of Bipolar FAST™/AS/S
• 64mA Output Sink Current (74 Series)
• 48mA Output Sink Current (54 Series)
The CD54/74FCT245 is a noninverting, three-state, bidirec-
tional transceiver/buffer intended for two-way transmission
from”A” bus to “B” bus or “B” bus to “A” bus. The logic level
present on the Direction Input (DIR) determines the data direc-
tion. When the Output Enable input is HIGH, the outputs are in
the high impedance state.
• Output Voltage Swing Limited to 3.7V at V
• Controlled Output Edge Rates
= 5V
CC
• Input/Output Isolation to V
CC
• BiCMOS Technology with Low Quiescent Power
Ordering Information
TEMP.
RANGE ( C)
0 to 70
PKG.
NO.
o
PART NUMBER
CD74FCT245E
CD74FCT245M
CD54FCT245E
PACKAGE
20 Ld PDIP
20 Ld SOIC
E20.3
0 to 70
M20.3
E20.3
-55 to 125 20 Ld PDIP
NOTE: When ordering the suffix M and SM packages, use the entire
part number. Add the suffix 96 to obtain the variant in the tape and reel.
Pinout
CD54FCT245, CD74FCT245
(PDIP, SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
9
V
DIR
A0
A1
A2
A3
A4
A5
A6
A7
20
19
CC
OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12
B6
GND 10
11 B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
1
FAST™ is a trademark of Fairchild Semiconductor.
Copyright © 1999, Texas Instruments Incorporated
CD54FCT245, CD74FCT245
Functional Diagram
18
17
16
15
14
13
12
11
2
3
4
5
6
7
8
9
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
1
19
DIR
OE
GND = PIN 10
= PIN 20
V
CC
TRUTH TABLE (NOTE 1)
CONTROL INPUTS
OE
L
DIR
L
OPERATION
B Data to A Bus
L
H
A Data to B Bus
Isolation
H
X
NOTES:
1. H = High Voltage Level
L = Low Voltage Level
X = Irrelevant
2. To prevent excess currents in the High-Z (isolation) modes, all I/O terminals should be terminated
with 10kΩ to 1 MΩ resistors.
IEC Logic Symbol
CD74FCT245, CD54FCT245
19
1
G3
3EN1
3EN1
1
2
18
17
16
15
14
13
12
11
2
3
4
5
6
7
8
9
2
CD54FCT245, CD74FCT245
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage (V ). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.0V
CC
Thermal Resistance (Typical, Note 3)
θJA ( C/W)
DC Input Diode Current, I (for V < -0.5V) . . . . . . . . . . . . . . -20mA
IK
I
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
69
58
DC Output Diode Current, I
(for V < -0.5V) . . . . . . . . . . . -50mA
OK
DC Output Sink Current per Output Pin, I . . . . . . . . . . . . . . .70mA
O
o
O
o
o
DC Output Source Current per Output Pin, I . . . . . . . . . . . . -30mA
O
o
DC V
Current (I ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140mA
CC
CC
DC Ground Current (I
GND
). . . . . . . . . . . . . . . . . . . . . . . . . . .528mA
(SOIC Lead Tips Only)
Operating Conditions
o
o
Operating Temperature Range (T ) . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
o
o
CD74 Series, T = 0 C to 70 C . . . . . . . . . . . . . . .4.75V to 5.25V
A
o
o
CD54 Series,T = -55 C to 125 C . . . . . . . . . . . . . . .4.5V to 5.5V
A
DC Input Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
I
CC
CC
DC Output Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ V
O
Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is calculated in accordance with JESD 51.
JA
o
o
Electrical Specifications 74FCT Commercial Temperature Range 0 C to 70 C, V
Max = 5.25V, V
Min = 4.75V
CC
CC
o
o
54FCT Extended Industrial Temperature Range -55 C to 125 C; V
Max = 5.5V, V
Min = 4.5V
CC
CC
AMBIENT TEMPERATURE (T )
A
TEST
CONDITIONS
o
o
o
o
o
25 C
0 C TO 70 C -55 C TO 125 C
PARAMETER
SYMBOL
V
I
(mA)
V (V)
CC
MIN
MAX
MIN
MAX
MIN
MAX UNITS
I
O
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
4.5 to 5.5
4.5 to 5.5
Min
2
-
0.8
-
2
-
0.8
-
2
-
0.8
-
V
V
IH
V
-
-
-
IL
V
V
V
or
-15
-12
64
2.4
2.4
-
V
OH
IH
V
Min
2.4
-
-
-
2.4
-
V
IL
Low Level Output Voltage
V
or
Min
-
0.55
0.55
0.1
-0.1
0.5
-0.5
-
-
0.55
-
-
-
V
OL
IH
V
48
Min
-
-
-
0.55
1
V
IL
High Level Input Current
Low Level Input Current
I
V
Max
-
-
1
-
µA
µA
µA
µA
mA
IH
CC
I
GND
Max
-
-
-
-
-1
10
-10
-
-
-
-1
10
-10
-
IL
Three-State Leakage
Current
I
V
Max
OZH
CC
I
GND
Max
-
-
-
OZL
Short Circuit Output Current
(Note 4)
I
V
or
Max
-60
-60
-60
OS
CC
GND
V
= 0
O
Input Clamp Voltage
V
V
GND
or
-18
0
Min
Max
Max
-
-
-
-1.2
8
-
-
-
-1.2
80
-
-
-
-1.2
500
2
V
IK
CC
Quiescent Supply Current,
MSI
I
V
or
µA
mA
CC
CC
GND
Additional Quiescent Supply
Current per Input Pin TTL In-
puts High, 1 Unit Load
∆I
3.4V
(Note 5)
1.6
1.6
CC
NOTES:
4. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.
5. Inputs that are not measured are at V or GND.
CC
6. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆I
o
limit specified in Static Characteristics Chart, e.g., 1.6mA Max at 70 C.
CC
3
CD54FCT245, CD74FCT245
Switching Specifications t , t = 2.5ns, C = 50pF, R - See Figure 3
r
f
L
L
AMBIENT TEMPERATURE (T )
A
o
o
o
o
o
25 C
0 C TO 70 C
-55 C TO 125 C
V
CC
PARAMETER
Propagation Delays
SYMBOL
(V)
TYP
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
t
, t
5
5
1.5
-
7
1.5
-
7.5
ns
PLH PHL
Data to Outputs)
Output Enable to Output
t
t
, t
PZL PZH
5
5
-
6
6
1.5
1.5
-
-
-
9.5
7.5
-
1.5
1.5
-
-
-
10
10
-
ns
ns
pF
Output Disable to Output
, t
PLZ PHZ
Power Dissipation
Capacitance
C
49
49
49
PD
Min (Valley) V
OHV
of Other Outputs (Output Under Test
Not Switching)
During Switching
V
5
5
0.5
1
-
-
-
-
-
-
-
-
-
-
-
-
V
V
OHV
Max (Peak) V
OLP
During Switching of
V
OLP
Other Outputs (Output Under Test Not
Switching)
Input Capacitance
C
-
-
-
-
-
-
-
-
10
15
-
-
-
-
10
15
pF
pF
l
Input/Output Capacitance
C
I/O
NOTES:
7. 5V: Min is at 5.5V, Max is at 4.5V.
o
o
o
o
5V: Min is at 5.25V for 0 C to 70 C, Max is at 4.75V for 0 C to 70 C, Typ is at 5V.
8. C , measured per function, is used to determine the dynamic power consumption.
PD
2
2
P
(per package) = V
I
+ ∑ (V
f C
+ V
f
C
+ V
∆l
D) where:
D
CC CC
= supply voltage
CC
l
PD
O
O
L
CC CC
V
∆l
CC
CC
= flow through current x unit load
= output load capacitance
C
L
D = duty cycle of input high
f
= output frequency
O
f = input frequency
I
4
CD54FCT245, CD74FCT245
Test Circuits and Waveforms
V
CC
SWITCH POSITION
t , t = 2.5ns
r
f
7V
TEST
SWITCH
Closed
Open
V
3V
0
I
(NOTE 9)
500Ω
V
0
t
, t
, Open Drain
, t , t
DEFINITIONS:
PLZ PZL
R
L
PULSE Z
GEN
O
DUT
t
, t
PHZ PZH PLH PHL
C
L
500Ω
R
T
R
50pF
L
R
= Z
T
O
C
= Load capacitance, includes jig and probe
capacitance.
L
R = Termination resistance, should be equal to Z
of
NOTE:
9. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; Z
T
OUT
the Pulse Generator.
≤ 50Ω;
OUT
V
= 0V to 3V.
IN
Input: t = t = 2.5ns (10% to 90%), unless otherwise specified
t , t ≤ 2.5ns.
f
r
r
f
FIGURE 1. TEST CIRCUIT
3V
1.5V
0V
DATA
INPUT
t
SH
t
H
3V
1.5V
0V
TIMING
INPUT
t
REM
ASYNCHRONOUS CONTROL
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
1.5V
t
SYNCHRONOUS CONTROL
W
PRESET CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
t
SH
t
H
FIGURE 2. SETUP, HOLD, AND RELEASE TIMING
FIGURE 3. PULSE WIDTH
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL INPUT
1.5V
0V
t
t
PHL
PLH
t
t
PLZ
PZL
3.5V
1.5V
3.5V
V
OH
SWITCH
CLOSED
OUTPUT
NORMALLY LOW
1.5V
OUTPUT
0.3V
0.3V
V
V
OL
OL
t
t
PHL
t
t
PLH
PZH
PHZ
V
OH
3V
OUTPUT
NORMALLY HIGH
SWITCH
OPEN
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
1.5V
0V
0V
FIGURE 4. ENABLE AND DISABLE TIMING
FIGURE 5. PROPAGATION DELAY
5
Test Circuits and Waveforms (Continued)
V
OH
OTHER
OUTPUTS
V
OL
V
OH
OUTPUT
UNDER
TEST
V
OHV
V
OLP
V
OL
NOTES:
10. V
OLP
is measured with respect to a ground reference near the output under test. V
OHV
is measured with respect to V .
OH
11. Input pulses have the following characteristics:
≤ 1MHz, t = 2.5ns, t = 2.5ns, skew 1ns.
P
RR
r
f
12. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.
FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
6
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Copyright 1999, Texas Instruments Incorporated
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