CD74FCT373ATE [TI]
FCT Interface Logic Octal Transparent Latch, Three-State; FCT接口逻辑八路透明锁存器,三态型号: | CD74FCT373ATE |
厂家: | TEXAS INSTRUMENTS |
描述: | FCT Interface Logic Octal Transparent Latch, Three-State |
文件: | 总2页 (文件大小:19K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD54/74FCT373,
CD54/74FCT373AT,
Data sheet acquired from Harris Semiconductor
SCHS272
CD54/74FCT533
FCT Interface Logic
Octal Transparent Latch, Three-State
February 1996
Features
Description
• CD54/74FCT373, CD54/74FCT373AT - Non-Inverting
The CD54/74FCT373, 373AT, and 533 octal transparent
latches use a small-geometry BiCMOS technology. The output
stage is a combination of bipolar and CMOS transistors that
limits the output-HIGH level to two diode drops below VCC. This
resultant lowering of output swing (0V to 3.7V) reduces power
bus ringing (a source of EMI) and minimizes VCC bounce and
ground bounce and their effects during simultaneous output
switching. The output configuration also enhances switching
speed and is capable of sinking 32mA to 48mA.
• CD54/74FCT533 - Inverting
• Buffered inputs
• Typical Propagation Delay: 3.9ns at VCC = 5V,
o
TA = +25 C, CL = 50pF (FCT373AT)
• SCR-Latchup-Resistant BiCMOS Process and Circuit
Design
The CD54/74FCT373, 373AT, and 533 outputs are transpar-
ent to the inputs when the Latch Enable (LE) is HIGH. When
the Latch Enable (LE) goes LOW, the data is latched. The
Output Enable (OE) controls the three-state outputs. When
the Output Enable (OE) is HIGH, the outputs are in the high-
impedance state. The latch operation is independent of the
state of the Output Enable.
• FCTXXX Types - Speed of Bipolar FAST®/AS/S;
FCTXXXAT Types - 30% Faster than FAST/AS/S with
Significantly Reduced Power Consumption
• 48mA to 32mA Output Sink Current (Commercial/
Extended Industrial)
• Output Voltage Swing Limited to 3.7V at VCC = 5V
• Controlled Output-Edge Rates
Ordering Information
o
PART NUMBER
CD54/74FCT373E
CD54/74FCT373ATE
CD54/74FCT533E
CD54/74FCT373M
CD54/74FCT373ATM
CD54/74FCT533M
CD54/74FCT373SM
CD54/74FCT533SM
CD54FCT373H
TEMP. RANGE ( C)
PACKAGE
• Input/Output Isolation to VCC
-55 to 125, 0 to 70 20 Ld PDIP
-55 to 125, 0 to 70 20 Ld PDIP
-55 to 125, 0 to 70 20 Ld PDIP
-55 to 125, 0 to 70 20 Ld SOIC
-55 to 125, 0 to 70 20 Ld SOIC
-55 to 125, 0 to 70 20 Ld SOIC
-55 to 125, 0 to 70 20 Ld SSOP
-55 to 125, 0 to 70 20 Ld SSOP
-55 to 125
• BiCMOS Technology with Low Quiescent Power
CD54FCT533H
-55 to 125
Functional Diagram
TRUTH TABLE
373
533
OUTPUT
ENABLE
LATCH
ENABLE
373,373AT
OUTPUT
533
OUTPUT
3
4
2
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DATA
5
7
6
L
L
L
L
H
H
H
L
H
L
I
H
L
L
H
H
L
8
9
13
14
17
18
12
15
16
19
L
L
h
X
H
Z
X
Z
11
1
LE
H = HIGH voltage level.
L = LOW voltage level.
X = Irrelevant.
I = LOW voltage level one setup time
prior to the high-to-low latch enable
transition.
OE
Z = HIGH Impedance.
h = HIGH voltage level one setup time
prior to the high-to-low latch enable
transition.
FAST® is a registered trademark of Fairchild Semiconductor Corporation.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 2230.2
Copyright © Harris Corporation 1996
1
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