CD74HC03M96E4 [TI]
High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain; 高速CMOS逻辑四路2输入与非门与漏极开路型号: | CD74HC03M96E4 |
厂家: | TEXAS INSTRUMENTS |
描述: | High-Speed CMOS Logic Quad 2-Input NAND Gate with Open Drain |
文件: | 总13页 (文件大小:415K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD54HC03, CD74HC03,
CD54HCT03, CD74HCT03
Data sheet acquired from Harris Semiconductor
SCHS126D
High-Speed CMOS Logic
February 1998 - Revised September 2003
Quad 2-Input NAND Gate with Open Drain
Features
Description
• Buffered Inputs
The ’HC03 and ’HCT03 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The HCT logic family is functionally as well as
pin compatible with the standard LS logic family.
• Typical Propagation Delay: 8ns at V
o
= 5V,
[ /Title
(CD74H
C03,
CC
C = 15pF, T = 25 C
L
A
• Output Pull-up to 10V
CD74H
CT03)
/Subject
(High
• Fanout (Over Temperature Range)
These open drain NAND gates can drive into resistive loads
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
to output voltages as high as 10V. Minimum values of R
required versus load voltage are shown in Figure 2.
L
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
Speed
CMOS
Logic
Quad 2-
Input
TEMP. RANGE
o
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
CD54HC03F3A
CD54HCT03F3A
CD74HC03E
( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
CD74HC03M
• HCT Types
CD74HC03MT
CD74HC03M96
CD74HCT03E
CD74HCT03M
CD74HCT03MT
CD74HCT03M96
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC03, CD54HCT03
(CERDIP)
CD74HC03, CD74HCT03
(PDIP, SOIC)
TOP VIEW
1A
1B
1
2
3
4
5
6
7
14 V
CC
13 4B
12 4A
11 4Y
10 3B
1Y
2A
2B
2Y
9
8
3A
3Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC03, CD74HC03, CD54HCT03, CD74HCT03
Functional Diagram
1
2
3
6
8
1A
1B
1Y
2Y
4
5
2A
2B
9
3A
3B
3Y
4Y
10
12
13
11
4A
4B
GND = 7
= 14
V
CC
TRUTH TABLE
A
L
B
L
Y
Z (Note 1)
Z (Note 1)
Z (Note 1)
L
H (Note 2)
H (Note 2)
H (Note 2)
L
H
L
L
H
H
H
NOTES:
1. Without pull-up (high impedance)
2. Requires pull-up (R to V )
L
L
Logic Symbol
nA
nB
nY
2
CD54HC03, CD74HC03, CD54HCT, CD74HCT03
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
JA
CC
DC Input Diode Current, I
For V < -0.5V or V > V
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
o
DC Output Source or Sink Current per Output Pin, I
O
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
DC Drain Current, per Output, I
O
(SOIC - Lead Tips Only)
For -0.5V < V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25mA
O
DC V
CC
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
4.5
3.15
-
3.15
3.15
6
2
4.2
-
4.2
-
4.2
-
Low Level Input
Voltage
V
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
0.1
0.1
0.1
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
0.1
0.1
0.1
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
0.1
0.1
0.1
-
IL
4.5
6
Low Level Output
Voltage
CMOS Loads
V
V
or
0.02
0.02
0.02
-
2
OL
IH
V
IL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
2
-
20
-
40
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
2
-
-
2
-
-
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
0.8
0.8
0.8
IL
3
CD54HC03, CD74HC03, CD54HCT03, CD74HCT03
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Low Level Output
V
V
or
IH
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
OL
Voltage CMOS Loads
V
IL
Low Level Output
Voltage
TTL Loads
4
4.5
5.5
5.5
-
-
0.26
-
-
0.33
-
-
0.4
V
Input Leakage
Current
I
V
and
GND
-
-
±0.1
±1
±1
µA
I
CC
Quiescent Device
Current
I
V
or
0
-
-
-
-
2
-
-
20
-
-
40
µA
µA
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 4)
V
4.5 to
5.5
100
360
450
490
CC
- 2.1
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
nA, nB
UNIT LOADS
1
NOTE: Unit Load is ∆I
tions table, e.g., 360µA max at 25 C.
limit specified in DC Electrical Specifica-
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Propagation Delay,
Input to Output (Figure 1)
t
, t
PLH PHL
C = 50pF
2
4.5
6
-
-
-
-
-
-
100
20
17
-
-
-
-
-
125
25
21
-
-
-
-
-
150
30
26
-
ns
ns
ns
ns
L
-
Propagation Delay, Data Input to
Output Y
t , t
PLH PHL
C = 15pF
5
8
L
Transition Times (Figure 1)
t
, t
TLH THL
C = 50pF
L
2
4.5
6
-
-
-
-
-
-
75
15
13
10
-
-
-
-
-
-
95
19
16
10
-
18
-
110
22
19
10
-
ns
ns
ns
pF
pF
-
-
-
Input Capacitance
C
-
-
-
-
-
I
Power Dissipation Capacitance
(Notes 5, 6)
C
5
6.4
-
PD
HCT TYPES
Propagation Delay,
Input to Output (Figure 1)
t
, t
PLH PHL
C = 50pF
4.5
5
-
-
-
24
-
-
-
30
-
-
-
36
-
ns
ns
L
Propagation Delay, Data Input to
Output Y
t , t
PLH PHL
C = 15pF
9
L
Transition Times (Figure 1)
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
-
-
-
-
15
10
-
-
19
10
-
-
22
10
ns
C
-
pF
I
4
CD54HC03, CD74HC03, CD54HCT03, CD74HCT03
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Power Dissipation Capacitance
(Notes 5, 6)
C
-
5
-
9
-
-
-
-
-
pF
PD
NOTES:
5. C
is used to determine the dynamic power consumption, per gate.
PD
6. P = C
2
2
2
V
f + Σ (C V
f ) + Σ (V /R ) (Duty Factor “Low”)
o L L
D
PD CC
i
L
CC
where f = input frequency, f = output frequency, C = output load capacitance, V
= supply voltage, Duty Factor “Low” = percent of
i
o
L
CC
time output is “low”, V = output voltage, R = pull-up resistor.
L
L
Test Circuits and Waveforms
800
700
600
500
400
300
200
100
INPUT LEVEL
V
L
0.8V (HCT V MAX)
IL
V
V
S
≤ 1.35V (HC V MAX)
S
IL
R
L
0.26V
4mA
R
MAX =
=
ON
t
V
PZL
O
t
PLZ
o
HCT
65Ω AT 25 C
V
R
OH
ON
90%
10%
nY
V
OL
t
THL
V
= 5V
V
CC
±10%
L
OUTPUT
LOW
OUTPUT
OFF
OUTPUT
LOW
HC
R
L
1kΩ
HC/HCT03
V
O
V
nA(nB)
nB(nA)
OPEN
DRAIN
NAND
GATE
CC
50pF
0
1
2
3
4
5
6
7
8
9
10
V
CC
V , LOAD VOLTAGE (V)
L
FIGURE 1. TRANSITION TIMES, PROPAGATION DELAY
TIMES, AND TEST CIRCUIT
FIGURE 2. MINIMUM RESISTIVE LOAD vs LOAD VOLTAGE
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
PDIP
Drawing
CD54HC03F
CD54HC03F3A
CD54HCT03F3A
CD74HC03E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
14
14
14
14
1
1
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
J
1
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC03EE4
CD74HC03M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
N
D
D
D
D
D
D
D
D
D
N
N
D
D
D
D
D
D
D
D
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC03M96
CD74HC03M96E4
CD74HC03M96G4
CD74HC03ME4
CD74HC03MG4
CD74HC03MT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC03MTE4
CD74HC03MTG4
CD74HCT03E
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT03EE4
CD74HCT03M
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT03M96
CD74HCT03M96E4
CD74HCT03M96G4
CD74HCT03ME4
CD74HCT03MG4
CD74HCT03MT
CD74HCT03MTE4
CD74HCT03MTG4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
CD74HC03M96
CD74HCT03M96
D
D
14
14
SITE 41
SITE 41
6.5
6.5
9.0
9.0
2.1
2.1
8
8
16
16
Q1
Q1
330
16
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
CD74HC03M96
CD74HCT03M96
D
D
14
14
SITE 41
SITE 41
346.0
346.0
346.0
346.0
33.0
33.0
Pack Materials-Page 2
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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