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CD74HC107EE4 [TI]

Dual J-K Flip-Flop with Reset Negative-Edge Trigger; 双JK触发器与复位负边沿触发
CD74HC107EE4
型号： CD74HC107EE4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Dual J-K Flip-Flop with Reset Negative-Edge Trigger
双JK触发器与复位负边沿触发

触发器
文件： 总15页 (文件大小：452K)
中文：  中文翻译
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CD54HC107, CD74HC107,  
CD74HCT107  
Data sheet acquired from Harris Semiconductor  
SCHS139D  
Dual J-K Flip-Flop with Reset  
Negative-Edge Trigger  
March 1998 - Revised October 2003  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise Immu-  
nity and Increased Input Rise and Fall Times  
The ’HC107 and CD74HCT107 utilize silicon gate CMOS  
technology to achieve operating speeds equivalent to LSTTL  
parts. They exhibit the low power consumption of standard  
CMOS integrated circuits, together with the ability to drive 10  
LSTTL loads.  
[ /Title  
(CD74  
HC107  
,
CD74  
HCT10  
7)  
/Sub-  
ject  
(Dual  
J-K  
Flip-  
Flop  
with  
Reset  
Nega-  
tive-  
• Asynchronous Reset  
• Complementary Outputs  
• Buffered Inputs  
These flip-flops have independent J, K, Reset and Clock  
inputs and Q and Q outputs. They change state on the  
negative-going transition of the clock pulse. Reset is  
accomplished asynchronously by a low level input.  
• Typical f  
MAX  
= 60MHz at V = 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
• Fanout (Over Temperature Range)  
This device is functionally identical to the HC/HCT73 but  
differs in terminal assignment and in some parametric limits.  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
The HCT logic family is functionally as well as pin compatible  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C with the standard LS family.  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
o
PART NUMBER  
CD54HC107F3A  
CD74HC107E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
• HC Types  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC107M  
at V  
= 5V  
CC  
CD74HC107MT  
CD74HC107M96  
CD74HCT107E  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
Pinout  
CD54HC107 (CERDIP)  
CD74HC107 (PDIP, SOIC)  
CD74HCT107 (PDIP)  
TOP VIEW  
1J  
1Q  
1
2
3
4
5
6
7
14 V  
CC  
13 1R  
12 1CP  
11 2K  
10 2R  
1Q  
1K  
2Q  
2Q  
9
8
2CP  
2J  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD54HC107, CD74HC107, CD74HCT107  
Functional Diagram  
1
3
1J  
1Q  
4
FF 1  
2
1K  
1Q  
12  
13  
1CP  
1R  
8
11  
9
5
6
2J  
2K  
2Q  
2Q  
FF 2  
2CP  
GND = 7  
= 14  
10  
2R  
V
CC  
TRUTH TABLE  
INPUTS  
OUTPUTS  
R
L
CP  
X
↓
J
X
L
K
Q
Q
X
L
L
H
H
H
H
H
H
No Change  
↓
H
L
L
H
L
L
↓
H
H
X
H
↓
H
X
Toggle  
H
No Change  
H= High Level (Steady State)  
L= Low Level (Steady State)  
X= Irrelevant  
↓
= High-to-Low Transition  
Logic Diagram  
1 (8)  
J
3 (5)  
Q
J
4(11)  
K
K
CL  
CL  
12 (9)  
2 (6)  
Q
A  
CP  
R
R
13 (10)  
2
CD54HC107, CD74HC107, CD74HCT107  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Thermal Resistance (Typical, Note 1)  
θ
( C/W)  
CC  
DC Input Diode Current, I  
JA  
IK  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .  
80  
86  
For V < -0.5V or V > V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
I
I
CC  
o
DC Drain Current, per Output, I  
O
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
o
For -0.5V < V < V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA  
O
CC  
o
o
DC Output Diode Current, I  
OK  
For V < -0.5V or V > V  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
DC Output Source or Sink Current per Output Pin, I  
O
(SOIC - Lead Tips Only)  
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA  
CC  
CC  
Operating Conditions  
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
HC TYPES  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
High Level Input  
Voltage  
V
-
-
-
2
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
4.5  
3.15  
-
-
3.15  
-
-
3.15  
6
2
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
-0.02  
2
1.9  
1.9  
1.9  
OH  
IH  
V
IL  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
IH  
V
IL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
3
CD54HC107, CD74HC107, CD74HCT107  
DC Electrical Specifications (Continued)  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
4
-
40  
-
80  
µA  
CC  
CC  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
V
V
or  
IH  
-0.02  
4.5  
4.4  
4.4  
4.4  
OH  
V
IL  
CMOS Load  
High Level Output  
Voltage  
-4  
4.5  
3.98  
-
-
3.84  
-
3.7  
-
V
TTL Loads  
Low Level Output  
Voltage CMOS Loads  
V
V
V
or  
IH  
0.02  
4
4.5  
4.5  
-
-
-
-
0.1  
-
-
0.1  
-
-
0.1  
0.4  
V
V
OL  
IL  
Low Level Output  
Voltage  
0.26  
0.33  
TTL Loads  
Input Leakage  
Current  
I
V
and  
GND  
-
5.5  
5.5  
-
±0.1  
-
±1  
-
±1  
µA  
I
CC  
Quiescent Device  
Current  
I
V
or  
0
-
-
-
-
4
-
-
40  
-
-
80  
µA  
µA  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
(Note 2)  
V
4.5 to  
5.5  
100  
360  
450  
490  
CC  
- 2.1  
NOTE:  
2. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
INPUT  
All  
UNIT LOADS  
0.3  
NOTE: Unit Load is ∆I  
tions table, e.g., 360µA max at 25 C.  
limit specified in DC Electrical Specifica-  
CC  
o
Prerequisite For Switching Specifications  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
CP Pulse Width  
t
t
-
-
2
80  
16  
14  
80  
16  
14  
-
-
-
-
-
-
-
-
-
-
-
-
100  
20  
-
-
-
-
-
-
120  
24  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
w
4.5  
6
17  
20  
R Pulse Width  
2
100  
20  
120  
24  
w
4.5  
6
17  
20  
4
CD54HC107, CD74HC107, CD74HCT107  
Prerequisite For Switching Specifications (Continued)  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
125  
25  
21  
3
MAX  
MIN  
150  
30  
26  
3
MAX  
UNITS  
ns  
Setup Time, J, K to CP  
t
-
-
-
-
2
4.5  
6
100  
20  
17  
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SU  
ns  
ns  
Hold Time, J, K to CP  
Removal Time  
t
2
ns  
H
4.5  
6
3
3
3
ns  
3
3
3
ns  
t
2
60  
12  
10  
6
75  
15  
13  
5
90  
18  
15  
4
ns  
REM  
4.5  
6
ns  
ns  
CP Frequency  
f
2
MHz  
MHz  
MHz  
MAX  
4.5  
6
30  
35  
25  
29  
20  
23  
HCT TYPES  
CP Pulse Width  
t
t
-
-
-
-
-
-
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
18  
24  
20  
5
-
-
-
-
-
-
-
-
-
-
-
-
23  
30  
25  
5
-
-
-
-
-
-
27  
36  
30  
5
-
-
-
-
-
-
ns  
ns  
w
R Pulse Width  
w
Setup Time, J, K to CP  
Hold Time, J, K to CP  
Removal Time  
t
ns  
SU  
t
ns  
H
t
12  
28  
15  
22  
18  
19  
ns  
REM  
CP Frequency  
f
MHz  
MAX  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
MIN TYP MAX  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN  
MAX  
MIN  
MAX  
UNITS  
Propagation Delay,  
CP to Q  
t
t
t
, t  
C = 50pF  
2
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
170  
34  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
215  
43  
-
-
-
255  
51  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
MHz  
PLH PHL  
L
C = 15pF  
14  
-
-
L
C = 50pF  
6
29  
170  
34  
-
37  
215  
43  
-
-
43  
255  
51  
-
L
Propagation Delay,  
CP to Q  
, t  
PLH PHL  
C = 50pF  
2
-
-
L
4.5  
5
-
-
C = 15pF  
14  
-
-
L
C = 50pF  
6
29  
155  
31  
-
37  
195  
39  
-
-
43  
235  
47  
-
L
Propagation Delay,  
R to Q, Q  
, t  
PLH PHL  
C = 50pF  
2
-
-
L
4.5  
5
-
-
C = 15pF  
13  
-
-
L
C = 50pF  
6
26  
75  
15  
13  
10  
-
33  
95  
19  
16  
10  
-
-
40  
110  
22  
19  
10  
-
L
Output Transition Time  
t
, t  
TLH THL  
C = 50pF  
L
2
-
18  
-
4.5  
6
-
-
-
Input Capacitance  
CP Frequency  
C
-
-
-
-
I
f
C = 15pF  
5
60  
-
MAX  
L
5
CD54HC107, CD74HC107, CD74HCT107  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
Power Dissipation Capacitance  
(Notes 3, 4)  
C
-
5
-
31  
-
-
-
-
-
pF  
PD  
HCT TYPES  
Propagation Delay,  
CP to Q  
t
t
t
, t  
C = 50pF  
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
18  
-
43  
-
-
-
-
-
-
-
-
-
-
-
54  
-
-
-
-
-
-
-
-
-
-
-
65  
-
ns  
ns  
PLH PHL  
L
C = 15pF  
L
Propagation Delay,  
CP to Q  
, t  
PLH PHL  
CL = 50pF  
4.5  
5
40  
-
50  
-
60  
-
ns  
C = 15pF  
L
17  
-
ns  
Propagation Delay,  
R to Q, Q  
, t  
PLH PHL  
CL = 50pF  
4.5  
5
38  
-
48  
-
57  
-
ns  
C = 15pF  
16  
-
ns  
L
Output Transition Time  
Input Capacitance  
CP Frequency  
t
, t  
TLH THL  
C = 50pF  
L
4.5  
-
15  
10  
-
19  
10  
-
22  
10  
-
ns  
C
-
-
pF  
MHz  
pF  
I
f
C = 15pF  
L
5
56  
30  
MAX  
Power Dissipation Capacitance  
(Notes 3, 4)  
C
-
5
-
-
-
PD  
NOTES:  
3. C  
is used to determine the dynamic power consumption, per flip-flop.  
PD  
4. P = C  
2
2
V
f + Σ C V  
f where f = input frequency, f = output frequency, C = output load capacitance, V  
= supply voltage.  
D
PD CC  
i
L
CC  
o
i
o
L
CC  
Test Circuits and Waveforms  
I
t
+ t =  
WH  
WL  
I
t C = 6ns  
fC  
r
L
t
+ t  
=
L
WL  
WH  
t C = 6ns  
t C  
f
L
f
t C  
f
L
CL  
r
L
3V  
V
CC  
90%  
10%  
2.7V  
CLOCK  
CLOCK  
50%  
10%  
1.3V  
0.3V  
50%  
t
50%  
1.3V  
t
1.3V  
0.3V  
GND  
GND  
t
t
WH  
WL  
WH  
WL  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
CC  
CC  
CC  
CC  
accordance with device truth table. For f  
, input duty cycle = 50%.  
accordance with device truth table. For f  
, input duty cycle = 50%.  
MAX  
MAX  
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
t = 6ns  
t = 6ns  
t = 6ns  
t = 6ns  
r
f
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
6
CD54HC107, CD74HC107, CD74HCT107  
Test Circuits and Waveforms (Continued)  
t C  
t C  
t C  
t C  
r
L
f
L
f
L
r
L
V
3V  
CC  
90%  
10%  
2.7V  
0.3V  
CLOCK  
INPUT  
CLOCK  
INPUT  
50%  
1.3V  
GND  
GND  
t
t
t
t
H(L)  
H(H)  
H(H)  
H(L)  
V
3V  
CC  
DATA  
INPUT  
DATA  
INPUT  
50%  
1.3V  
t
SU(L)  
1.3V  
1.3V  
GND  
GND  
t
t
t
SU(H)  
SU(H)  
SU(L)  
t
t
90%  
50%  
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
90%  
1.3V  
OUTPUT  
OUTPUT  
10%  
10%  
t
t
t
PLH  
t
PHL  
PHL  
PLH  
t
REM  
t
REM  
V
3V  
CC  
SET, RESET  
OR PRESET  
SET, RESET  
OR PRESET  
50%  
1.3V  
GND  
GND  
IC  
IC  
C
C
L
L
50pF  
50pF  
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
7
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
CDIP  
CDIP  
PDIP  
Drawing  
5962-8515401CA  
9084901MCA  
ACTIVE  
OBSOLETE  
ACTIVE  
J
J
14  
14  
14  
14  
1
TBD  
TBD  
TBD  
A42 SNPB  
Call TI  
N / A for Pkg Type  
Call TI  
CD54HC107F3A  
CD74HC107E  
J
1
A42 SNPB  
N / A for Pkg Type  
ACTIVE  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HC107EE4  
CD74HC107M  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
N
D
D
D
D
D
D
D
D
D
N
N
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC107M96  
CD74HC107M96E4  
CD74HC107M96G4  
CD74HC107ME4  
CD74HC107MG4  
CD74HC107MT  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC107MTE4  
CD74HC107MTG4  
CD74HCT107E  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HCT107EE4  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Mar-2008  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) W1 (mm)  
(mm) (mm) Quadrant  
CD74HC107M96  
SOIC  
D
14  
2500  
330.0  
16.4  
6.5  
9.0  
2.1  
8.0  
16.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
11-Mar-2008  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SOIC 14  
SPQ  
Length (mm) Width (mm) Height (mm)  
346.0 346.0 33.0  
CD74HC107M96  
D
2500  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
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