CD74HC123PWRE4 [TI]
High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets; 高速CMOS逻辑双路可重触发单稳态触发器与复位型号: | CD74HC123PWRE4 |
厂家: | TEXAS INSTRUMENTS |
描述: | High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets |
文件: | 总17页 (文件大小:359K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD54/74HC123, CD54/74HCT123,
CD74HC423, CD74HCT423
Data sheet acquired from Harris Semiconductor
SCHS142F
High-Speed CMOS Logic Dual Retriggerable
Monostable Multivibrators with Resets
September 1997 - Revised October 2003
Features
Ordering Information
• Overriding Reset Terminates Output Pulse
• Triggering From the Leading or Trailing Edge
• Q and Q Buffered Outputs
o
PART NUMBER
CD54HC123F3A
CD54HCT123F3A
CD74HC123E
TEMP. RANGE ( C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
[ /Title
(CD74
HC123
,
CD74
HCT12
3,
CD74
HC423
,
CD74
HCT42
3)
• Separate Resets
• Wide Range of Output-Pulse Widths
• Schmitt Trigger on Both A and B Inputs
• Fanout (Over Temperature Range)
CD74HC123M
CD74HC123MT
CD74HC123M96
CD74HC123NSR
CD74HC123PW
CD74HC123PWR
CD74HC123PWT
CD74HC423E
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
CD74HC423M
- High Noise Immunity: N = 30%, N = 30%of V
IL IH
at
/Sub-
ject
(High
Speed
CC
CD74HC423MT
CD74HC423M96
CD74HC423NSR
CD74HCT123E
CD74HCT123M
CD74HCT123MT
CD74HCT123M96
CD74HCT423E
CD74HCT423MT
CD74HCT423M96
V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Description
The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are
dual monostable multivibrators with resets. They are all
retriggerable and differ only in that the 123 types can be
triggered by a negative to positive reset pulse; whereas the
423 types do not have this feature. An external resistor (R )
X
and an external capacitor (C ) control the timing and the
X
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
accuracy for the circuit. Adjustment of Rx and C provides a
X
wide range of output pulse widths from the Q and Q
terminals. Pulse triggering on the A and B inputs occur at a
particular voltage level and is not related to the rise and fall
times of the trigger pulses.
Once triggered, the output pulse width may be extended by
retriggering inputs A and B. The output pulse can be
terminated by a LOW level on the Reset (R) pin. Trailing
edge triggering (A) and leading edge triggering (B) inputs
are provided for triggering from either edge of the input
pulse. If either Mono is not used each input on the unused
device (A, B, and R) must be terminated high or low.
The minimum value of external resistance, Rx is typically
5kΩ. The minimum value external capacitance, CX, is 0pF.
The calculation for the pulse width is t = 0.45 R C at
W
X X
V
= 5V.
CC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
Pinout
Functional Diagram
CD54HC123, CD54HCT123
1Cx
1Rx
(CERDIP)
CD74HC123
(PDIP, SOIC, SOP, TSSOP)
CD74HC423
(PDIP, SOIC, SOP)
CD74HCT123, CD74HCT423
(PDIP, SOIC)
V
CC
14
1Cx
15
1RxCx
13
4
1A
1Q
1Q
1
2
MONO 1
1B
1R
TOP VIEW
3
1A
1B
1R
1Q
2Q
1
2
3
4
5
6
7
8
16 V
CC
11
2R
2A
15 1R C
X
X
5
9
14 1C
X
2Q
2Q
13 1Q
12 2Q
11 2R
10 2B
MONO 2
12
10
2B
2Cx
2RxCx
7
2C
X
X
6
2R C
V
X
CC
2Cx
2Rx
9
2A
GND
TRUTH TABLE
R
INPUTS
B
OUTPUTS
A
Q
Q
CD74HC/HCT123
H
X
L
X
L
↑
H
H
H
L
L
H
H
↓
H
H
X
L
X
H
L
L
H
↑
CD74HC/HCT423
H
X
L
X
L
↑
H
H
H
L
L
H
H
↓
H
X
H
L
X
L
H
H = High Voltage Level, L = Low Voltage Level,
X = Don’t Care.
2
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Package Thermal Impedance, θ (see Note 1):
JA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
CC
DC Input Diode Current, I
For V < -0.5V or V > V
o
IK
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
o
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
o
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All
UNIT LOADS
0.35
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.
CC
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V) MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
Minimum Input,
Pulse Width
t
WL
A
2
100
-
-
-
-
-
-
-
-
-
-
-
-
125
25
-
-
-
-
-
-
-
-
-
-
-
-
150
30
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
4.5
6
20
17
21
26
B
t
2
100
20
125
25
150
30
WH
4.5
6
17
21
26
4
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V) MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
R
t
2
100
-
-
-
-
-
-
-
-
-
-
-
-
-
125
25
21
65
13
11
65
13
11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
150
30
26
75
15
13
75
15
13
-
-
-
150
30
26
75
15
13
75
15
13
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WL
4.5
6
20
17
50
10
9
-
-
-
A and B Hold Time
t
2
-
-
-
H
4.5
6
-
-
-
-
-
-
Reset Removal Time
Retrigger Time Number
t
2
50
10
9
-
-
-
REM
4.5
6
-
-
-
-
-
-
t
t
5
-
-
-
-
rT
W
R
= 10KΩ, C = 0
-
50
-
63
-
76
-
X
X
Output Pulse Width
Q or Q
5
5
R
= 10KΩ, C = 10nF
40
-
50
38.7
-
51.3
38.2
-
51.8
µs
X
X
HCT TYPES
Minimum Input,
Pulse Width
-
t
WL
A
20
20
20
10
10
-
-
-
-
-
-
-
-
-
-
25
25
25
13
13
-
-
-
-
-
-
-
-
-
-
30
30
30
15
15
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
B
t
WH
R
t
WL
A and B Hold Time
Reset Removal Time
t
5
5
H
t
REM
Retrigger Time Number
(Note 3)
R
= 10KΩ, C = 0
t
t
5
5
-
50
-
-
-
63
-
-
-
76
-
-
ns
X
X
rT
Output Pulse Width Q or Q
= 10KΩ, C = 10nF
40
50
38.7
51.3
38.2
51.8
µs
W
R
X
X
NOTE:
3. Time to trigger depends on the values of R and C . The output pulse width can only be extended when the time between the active-
X
X
going edges of the trigger input pulses meet the minimum retrigger time requirement.
5
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
Switching Specifications Input t , t = 6ns, R = 10KΩ, C = 0
r
f
X
X
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
UNIT
S
PARAMETER
HC TYPES
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX
CC
Trigger Propagation Delay
A, B, R to Q
t
C
= 50pF
PLH
L
2
-
-
-
300
60
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
375
75
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
450
90
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
C
C
= 15pF
= 50pF
= 50pF
25
-
L
L
L
6
51
320
64
-
64
400
80
-
76
480
96
-
A, B, R to Q
t
2
-
PHL
4.5
5
-
C
C
C
= 15pF
= 50pF
= 50pF
26
-
L
L
L
6
54
215
43
37
75
15
13
-
68
270
54
46
95
19
16
-
82
325
65
55
110
22
19
-
Reset Propagation Delay
R to Q or Q
t
, t
2
-
PHL PLH
4.5
6
-
-
Output Transition Time
t
, t
C
= 50pF
2
-
THL TLH
L
4.5
6
-
-
Output Pulse Width
-
-
-
-
5
45
R
= 10KΩ, C = 10nF
X
X
Pulse Width Match Between
Circuits In the Same Package
5
-
±2
-
-
-
-
-
%
R
= 10KΩ, C = 10pF
X
X
Power Dissipation Capacitance
(Note 4)
C
C
C
= 15pF
= 50pF
5
-
-
-
-
-
-
-
-
-
-
-
pF
pF
PD
L
Input Capacitance
C
10
10
10
10
IN
L
HCT TYPES
Trigger Propagation Delay
A, B, R to Q
t
C
C
C
= 50pF
= 15pF
= 50pF
4.5
5
-
-
-
-
25
-
60
-
-
-
-
75
-
-
-
-
90
-
ns
ns
ns
PLH
L
L
L
A, B, R to Q
t
4.5
68
85
102
PHL
C
=15pF
= 50pF
5
-
-
27
-
-
-
-
-
-
-
-
ns
ns
L
Reset Propagation Delay
R to Q or Q
t
, t
C
4.5
48
60
72
PHL PLH
L
Output Transition Time
Output Pulse Width
t
, t
C
= 50pF
-
4.5
5
-
-
-
15
-
-
-
19
-
-
-
22
-
ns
THL TLH
L
-
45
µs
R
= 10KΩ, C = 10nF
X
X
6
CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423
Switching Specifications Input t , t = 6ns, R = 10KΩ, C = 0 (Continued)
r
f
X
X
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
UNIT
S
PARAMETER
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX
CC
Pulse Width Match Between
Circuits In the Same Package
-
-
5
±2
-
-
-
-
-
%
R
= 10KΩ, C = 10pF
X
X
Input Capacitance
NOTE:
C
C
= 50pF
-
-
-
10
-
10
-
10
pF
IN
L
4. C
P
is used to determine the dynamic power consumption, per multivibrator.
PD
= (C
2
2
+ C ) V
f ∑(C V
f )
CC O
D
PD
X
CC
i
L
Where
f = input frequency
i
f
= Output Frequency
O
C
C
= Output Load Capacitance
= External Capacitance
L
X
V
= Supply Voltage,
CC
I
assuming f «
i
------
t
W
7
Test Circuits and Waveforms
A
B = LOW
A = HIGH
A
B = LOW
A = HIGH
B
R
B
R
V
S
V
S
t
W
t
t
W
W
V
S
V
S
Q
Q
t
t
t
t
W
W
W
W
FIGURE 1. OUTPUT PULSE CONTROL USING RESET INPUT
(R) PULSE FOR 123
FIGURE 2. OUTPUT PULSE CONTROL USING RESET INPUT
(R) FOR 423
A
B
t
W
B
A
(R = HIGH)
t
rT
V
S
Q
t
W
t
t
W
W
NOTE: Output pulse control using retrigger pulse for 123 and 423.
FIGURE 3. TRIGGERING OF ONE SHOT BY INPUT A OR INPUT B FOR A PERIOD t
W
8
6
4
0.9
EXTERNAL CAPACITANCE (C ) = 10nF
X
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
EXTERNAL RESISTANCE (R ) = 10kΩ TO 100kΩ
X
2
o
3
2
1
AMBIENT TEMPERATURE (T ) = 25 C
A
10
10
10
8
6
4
2
HCT
8
6
4
2
8
6
4
DC SUPPLY VOLTAGE (V ) = 5V
CC
o
AMBIENT TEMPERATURE (T ) = 25 C
A
2
2
4
6 8
10
2
4
6 8
2
4
6 8
2
4 6 8
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
10
10
10
10
EXTERNAL CAPACITANCE (C ) - pF
DC SUPPLY VOLTAGE (V ) - VOLTS
CC
X
FIGURE 4. TYPICAL OUTPUT PULSE WIDTH AS A FUNCTION
OF C FOR R = 10kΩ AND 100kΩ
FIGURE 5. TYPICAL “K” FACTOR AS A FUNCTION OF V
CC
X
X
8
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
CDIP
CDIP
PDIP
Drawing
5962-8684701EA
5962-8970001EA
CD54HC123F
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
16
16
16
1
1
TBD
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
J
1
CD54HC123F3A
CD54HCT123F3A
CD74HC123E
J
1
J
1
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC123EE4
CD74HC123M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
N
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC123M96
CD74HC123M96E4
CD74HC123ME4
CD74HC123MT
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC123MTE4
CD74HC123NSR
CD74HC123NSRE4
CD74HC123PW
CD74HC123PWE4
CD74HC123PWR
CD74HC123PWRE4
CD74HC123PWT
CD74HC123PWTE4
CD74HC423E
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
NS
PW
PW
PW
PW
PW
PW
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PDIP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC423EE4
CD74HC423M
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
SOIC
SOIC
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC423M96
CD74HC423M96E4
CD74HC423ME4
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Orderable Device
CD74HC423MT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC423MTE4
CD74HC423NSR
CD74HC423NSRE4
CD74HCT123E
SOIC
SO
D
NS
NS
N
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT123EE4
CD74HCT123M
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT123M96
CD74HCT123M96E4
CD74HCT123ME4
CD74HCT123MT
CD74HCT123MTE4
CD74HCT423E
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT423EE4
CD74HCT423M96
CD74HCT423M96E4
CD74HCT423MT
CD74HCT423MTE4
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号:
CD74HC125EX
Bus Driver, HC/UH Series, 4-Func, 1-Bit, True Output, CMOS, PDIP14, PACKAGE-14
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