CD74HC126M96 [TI]
High-Speed CMOS Logic Quad Buffer, Three-State; 高速CMOS逻辑四路缓冲器，三态
| 型号： | CD74HC126M96 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Quad Buffer, Three-State |
| 文件： | 总10页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54HC126, CD74HC126,
CD54HCT126, CD74HCT126
Data sheet acquired from Harris Semiconductor
SCHS144C
High-Speed CMOS Logic
Quad Buffer, Three-State
November 1997 - Revised September 2003
Features
Description
• Three-State Outputs
The ’HC126 and ’HCT126 contain four independent three-
state buffers, each having its own output enable input, which
when “low” puts the output in the high-impedance state.
• Separate Output Enable Inputs
[ /Title
(CD74
HC126
,
CD74
HCT12
6)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
TEMP. RANGE
o
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
PART NUMBER
CD54HC126F3A
CD54HCT126F3A
CD74HC126E
( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Significant Power Reduction Compared to LSTTL
Logic ICs
/Sub-
ject
• HC Types
(High
Speed
CMOS
Logic
Quad
Buffer,
Three-
State)
- 2V to 6V Operation
CD74HC126M
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
CD74HC126MT
CD74HC126M96
CD74HCT126E
CD74HCT126M
CD74HCT126MT
CD74HCT126M96
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC126, CD54HC126
(CERDIP)
CD74HC126, CD74HC126
(PDIP, SOIC)
TOP VIEW
1OE
1A
1
2
3
4
5
6
7
14 V
CC
13 4OE
12 4A
1Y
2OE
2A
11 4Y
10 3OE
2Y
9
8
3A
3Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC126, CD74HC126, CD54HCT126, CD74HCT126
Functional Diagram
1
2
1OE
1A
3
1Y
2Y
3Y
4Y
4
2OE
2A
6
5
10
9
3OE
3A
8
13
12
4OE
4A
11
GND = 7
V
= 14
CC
TRUTH TABLE
INPUTS
OUTPUTS
nA
H
nOE
H
nY
H
L
L
H
X
L
Z
H= High Voltage Level
L= Low Voltage Level
X= Don’t Care
Z= High Impedance, OFF State
Logic Diagram
P
n
nA
nY
nOE
2
CD54HC126, CD74HC126, CD54HCT126, CD74HCT126
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
80
86
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±70mA
CC
CC
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-6
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-7.8
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
7.8
Input Leakage
Current
I
V
or
-
6
-
-
±0.1
-
±1
-
±1
µA
I
CC
GND
3
CD54HC126, CD74HC126, CD54HCT126, CD74HCT126
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Quiescent Device
Current
I
V
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
GND
Three-State Leakage
Current
I
V
V
or
IL
-
6
-
-
±0.5
-
±5
-
±10
µA
OZ
IH
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
6
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
Three-State Leakage
Current
I
V
V
or
IL
-
5.5
-
-
±0.5
-
±5
-
±10
µA
OZ
IH
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
nA, nOE
UNIT LOADS
1
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
CC
4
CD54HC126, CD74HC126, CD54HCT126, CD74HCT126
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
CONDITIONS
PARAMETER
HC TYPES
SYMBOL
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay Data
to Outputs
t
, t
C = 50pF
2
-
-
100
20
-
125
25
-
150
30
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
L
4.5
C = 15pF
L
5
6
2
8
-
CL = 50pF
17
125
25
-
21
155
31
-
36
190
38
-
Enable Delay Time
t
t
C = 50pF
-
PZL, PZH
L
4.5
5
-
C = 15pF
L
10
-
CL = 50pF
CL = 50pF
6
21
125
25
-
26
155
31
-
32
190
38
-
Disabling Delay Time
t
, t
2
-
PLZ PHZ
C = 50pF
4.5
5
-
L
C = 15pF
L
10
-
CL = 50pF
6
21
60
12
10
10
20
26
75
15
13
10
20
32
90
18
15
10
20
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
-
4.5
6
-
-
C
-
-
-
-
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
30
-
-
-
pF
PD
(Notes 3, 4)
HCT TYPES
Propagation Delay Time
to Outputs
t
, t
C = 50pF
4.5
5
-
9
-
24
-
30
-
36
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
L
C = 15pF
L
Output Enable Time
t
t
C = 50pF
4.5
5
25
-
31
-
38
-
PZL, PZH
L
C = 15pF
10
-
L
Output Disabling Time
t
, t
PLZ PHZ
C = 50pF
4.5
5
28
-
35
-
42
-
L
C = 15pF
11
-
L
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
12
10
20
15
10
20
18
10
20
C
-
-
-
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
36
-
-
-
pF
PD
(Notes 3, 4)
NOTES:
3. C
is used to determine the dynamic power consumption, per multiplexer.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
5
CD54HC126, CD74HC126, CD54HCT126, CD74HCT126
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 6. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 8. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 9. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 10. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
6
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