CD74HC138SM96 [TI]
HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, SSOP-16;
| 型号： | CD74HC138SM96 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, SSOP-16 驱动 输入元件 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总20页 (文件大小：765K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54/74HC138, CD54/74HCT138,
CD54/74HC238, CD54/74HCT238
Data sheet acquired from Harris Semiconductor
SCHS147I
High-Speed CMOS Logic 3- to 8-Line Decoder/
Demultiplexer Inverting and Noninverting
October 1997 - Revised August 2004
Features
Ordering Information
• Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
TEMP. RANGE
o
PART NUMBER
CD54HC138F3A
CD54HC238F3A
CD54HCT138F3A
CD54HCT238F3A
CD74HC138E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
[ /Title
(CD74
HC138
,
CD74
HCT13
8,
CD74
HC238
,
CD74
HCT23
8)
• l/O Port or Memory Selector
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Three Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13 ns at V
CC
= 5 V,
o
C = 15 pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
CD74HC138M
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
CD74HC138MT
CD74HC138M96
CD74HC238E
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
CD74HC238M
/Sub-
ject
(High
Speed
- 2 V to 6 V Operation
CD74HC238MT
CD74HC238M96
CD74HC238NSR
CD74HC238PW
CD74HC238PWR
CD74HC238PWT
CD74HCT138E
CD74HCT138M
CD74HCT138MT
CD74HCT138M96
CD74HCT238E
CD74HCT238M
CD74HCT238M96
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5 V
CC
• HCT Types
- 4.5-V to 5.5-V Operation
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
- Direct LSTTL Input Logic Compatibility,
V = 0.8 V (Max), V = 2 V (Min)
IL
IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Description
The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high-speed
silicon-gate CMOS decoders well suited to memory address
decoding or data-routing applications. Both circuits feature
low power consumption usually associated with CMOS
circuitry, yet have speeds comparable to low-power Schottky
TTL logic. Both circuits have three binary select inputs (A0,
A1, and A2). If the device is enabled, these inputs determine
which one of the eight normally high outputs of the
HC/HCT138 series go low or which of the normally low
outputs of the HC/HCT238 series go high.
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Two active low and one active high enables (E1, E2, and E3)
are provided to ease the cascading of decoders. The
decoder’s eight outputs can drive ten low-power Schottky
TTL equivalent loads.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Functional Diagram
Pinout
HC/HCT HC/HCT
CD54HC138, CD54HCT138, CD54HC238, CD54HCT238
238
138
(CERDIP)
CD74HC138, CD74HCT138, CD74HCT238
(PDIP, SOIC)
1
2
3
15
14
13
12
11
10
9
A0
A1
A2
Y0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
CD74HC238
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
A0
A1
1
2
3
4
5
6
7
8
16 V
CC
4
5
6
E1
E2
E3
15 Y0 (Y0)
14 Y1 (Y1)
13 Y2 (Y2)
12 Y3 (Y3)
11 Y4 (Y4)
10 Y5 (Y5)
A2
E1
E2
7
E3
(Y7) Y7
GND
9
Y6 (Y6)
Signal names in parentheses are for ’HC138 and ’HCT138.
TRUTH TABLE ’HC138, ’HCT138
INPUTS
ENABLE
ADDRESS
OUTPUTS
Y3 Y4
E3
X
E2
X
X
H
L
E1
A2
X
X
X
L
A1
X
X
X
L
A0
X
X
X
L
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
Y7
H
H
H
H
H
H
H
H
H
H
L
H
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
L
H
H
H
H
H
H
L
X
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
H
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
TRUTH TABLE ’HC238, ’HCT238
INPUTS
ENABLE
ADDRESS
OUTPUTS
Y3 Y4
E3
X
E2
X
X
H
L
E1
A2
X
X
X
L
A1
X
X
X
L
A0
X
X
X
L
Y0
L
Y1
L
Y2
L
Y5
L
Y6
L
Y7
L
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
X
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
L
L
L
H
H
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
L
L
H
L
L
L
L
H
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
2
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Package Thermal Impedance, θ (see Note 1):
JA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
CC
DC Input Diode Current, I
For V < -0.5V or V > V
o
IK
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
o
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
o
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems, theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
A0-A2
E1, E2
1.5
1.25
1
E3
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
Address to Output
t
t
C = 50pF
2
-
-
-
150
30
-
-
-
-
-
190
38
-
-
-
-
-
225
45
-
ns
ns
ns
ns
PLH, PHL
L
4.5
5
-
-
-
C = 15pF
13
-
L
C = 50pF
6
26
33
38
L
4
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-40 C TO
85 C
o
o
o
o
25 C
-55 C TO 125 C
TEST
PARAMETER
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Enable to Output
HC/HCT138
t
t
C = 50pF
2
-
-
-
150
30
26
75
15
13
-
-
-
-
-
-
-
-
190
38
33
95
19
16
-
-
-
-
-
-
-
-
265
53
45
110
22
19
-
ns
ns
ns
ns
ns
ns
pF
PLH, PHL
L
4.5
6
-
-
-
-
-
-
-
Output Transition Time
(Figure 1)
t
, t
TLH THL
C = 50pF
2
-
L
4.5
6
-
-
Power Dissipation
C
C = 15pF
L
5
67
PD
Capacitance (Notes 3, 4)
Input Capacitance
C
-
-
-
-
10
-
10
-
10
pF
IN
HCT TYPES
Propagation Delay
Address to Output
t
, t
PLH PHL
C = 50pF
4.5
5
-
-
-
-
14
-
35
-
-
-
-
44
-
-
-
-
53
-
ns
ns
ns
L
C = 15pF
L
Enable to Output
HC/HCT138
t
, t
PLH PHL
C = 50pF
4.5
35
44
53
L
Enable to Output
HC/HCT238
t
t
C = 15pF
4.5
4.5
5
-
-
-
-
-
-
40
15
-
-
-
-
-
50
19
-
-
-
-
-
60
22
-
ns
ns
pF
pF
PLH, PHL
L
Output Transition Time
(Figure 2)
t
, t C = 50pF
TLH THL L
Power Dissipation
Capacitance (Notes 3, 4)
C
C = 15pF
L
67
-
PD
Input Capacitance
NOTES:
C
-
-
10
10
10
IN
3. C
is used to determine the dynamic power consumption, per gate.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
t = 6ns
f
r
t = 6ns
f
t = 6ns
r
V
CC
3V
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
TLH
THL
t
t
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
t
t
PLH
PLH
PHL
PHL
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-8688401EA
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8688401EA
CD54HC238F3A
CD54HC138F
ACTIVE
ACTIVE
CDIP
CDIP
J
J
16
16
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
CD54HC138F
CD54HC138F3A
8406201EA
CD54HC138F3A
CD54HC238F3A
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8688401EA
CD54HC238F3A
CD54HCT138F
ACTIVE
ACTIVE
CDIP
CDIP
J
J
16
16
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
CD54HCT138F
CD54HCT138F3A
8550401EA
CD54HCT138F3A
CD54HCT238F3A
CD74HC138E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
J
16
16
16
16
16
16
16
16
16
16
16
1
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
5962-8974501EA
CD54HCT238F3A
N
N
D
D
D
D
D
D
D
D
25
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CD74HC138E
CD74HC138E
HC138M
CD74HC138EE4
CD74HC138M
25
Pb-Free
(RoHS)
N / A for Pkg Type
40
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CD74HC138M96
CD74HC138M96E4
CD74HC138M96G4
CD74HC138ME4
CD74HC138MG4
CD74HC138MT
CD74HC138MTE4
2500
2500
2500
40
Green (RoHS
& no Sb/Br)
HC138M
Green (RoHS
& no Sb/Br)
HC138M
Green (RoHS
& no Sb/Br)
HC138M
Green (RoHS
& no Sb/Br)
HC138M
40
Green (RoHS
& no Sb/Br)
HC138M
250
250
Green (RoHS
& no Sb/Br)
HC138M
Green (RoHS
& no Sb/Br)
HC138M
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
CD74HC138MTG4
CD74HC238E
ACTIVE
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
HC138M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
N
N
25
25
Pb-Free
(RoHS)
N / A for Pkg Type
CD74HC238E
CD74HC238E
HC238M
HC238M
HC238M
HC238M
HC238M
HC238M
HC238M
HC238M
HC238M
HC238M
HC238M
HC238M
HJ238
CD74HC238EE4
CD74HC238M
Pb-Free
(RoHS)
N / A for Pkg Type
D
40
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CD74HC238M96
CD74HC238M96E4
CD74HC238M96G4
CD74HC238ME4
CD74HC238MG4
CD74HC238MT
D
2500
2500
2500
40
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
40
Green (RoHS
& no Sb/Br)
D
250
250
250
2000
2000
2000
90
Green (RoHS
& no Sb/Br)
CD74HC238MTE4
CD74HC238MTG4
CD74HC238NSR
CD74HC238NSRE4
CD74HC238NSRG4
CD74HC238PW
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
NS
NS
NS
PW
PW
PW
Green (RoHS
& no Sb/Br)
SO
Green (RoHS
& no Sb/Br)
SO
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
CD74HC238PWE4
CD74HC238PWG4
90
Green (RoHS
& no Sb/Br)
HJ238
90
Green (RoHS
& no Sb/Br)
HJ238
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
CD74HC238PWR
CD74HC238PWRE4
CD74HC238PWRG4
CD74HC238PWT
CD74HC238PWTE4
CD74HC238PWTG4
CD74HCT138E
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PDIP
PW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
HJ238
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PW
PW
PW
PW
PW
N
2000
2000
250
250
250
25
Green (RoHS
& no Sb/Br)
HJ238
Green (RoHS
& no Sb/Br)
HJ238
Green (RoHS
& no Sb/Br)
HJ238
Green (RoHS
& no Sb/Br)
HJ238
Green (RoHS
& no Sb/Br)
HJ238
Pb-Free
(RoHS)
CD74HCT138E
CD74HCT138E
HCT138M
HCT138M
HCT138M
HCT138M
HCT138M
HCT138M
CD74HCT238E
CD74HCT238E
HCT238M
HCT238M
CD74HCT138EE4
CD74HCT138M
PDIP
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
SOIC
D
40
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
CD74HCT138M96
CD74HCT138M96E4
CD74HCT138M96G4
CD74HCT138ME4
CD74HCT138MG4
CD74HCT238E
SOIC
D
2500
2500
2500
40
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
40
Green (RoHS
& no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CD74HCT238EE4
CD74HCT238M
PDIP
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
SOIC
D
40
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CD74HCT238M96
SOIC
D
2500
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
CD74HCT238M96E4
CD74HCT238M96G4
CD74HCT238ME4
CD74HCT238MG4
CD74HCT238PW
ACTIVE
SOIC
SOIC
D
16
16
16
16
16
16
16
16
16
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
HCT238M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
2500
40
Green (RoHS
& no Sb/Br)
HCT238M
HCT238M
HCT238M
HK238
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
40
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
90
Green (RoHS
& no Sb/Br)
CD74HCT238PWE4
CD74HCT238PWG4
CD74HCT238PWR
CD74HCT238PWRE4
CD74HCT238PWRG4
90
Green (RoHS
& no Sb/Br)
HK238
90
Green (RoHS
& no Sb/Br)
HK238
2000
2000
2000
Green (RoHS
& no Sb/Br)
HK238
Green (RoHS
& no Sb/Br)
HK238
Green (RoHS
& no Sb/Br)
HK238
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC138, CD54HC238, CD54HCT138, CD54HCT238, CD74HC138, CD74HC238, CD74HCT138, CD74HCT238 :
Catalog: CD74HC138, CD74HC238, CD74HCT138, CD74HCT238
•
Automotive: CD74HC138-Q1, CD74HC138-Q1
•
Military: CD54HC138, CD54HC238, CD54HCT138, CD54HCT238
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC138M96
CD74HC238M96
CD74HC238NSR
CD74HC238PWR
CD74HC238PWT
CD74HCT138M96
CD74HCT238M96
CD74HCT238PWR
SOIC
SOIC
D
D
16
16
16
16
16
16
16
16
2500
2500
2000
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
12.4
12.4
16.4
16.4
12.4
6.5
6.5
8.2
6.9
6.9
6.5
6.5
6.9
10.3
10.3
10.5
5.6
2.1
2.1
2.5
1.6
1.6
2.1
2.1
1.6
8.0
8.0
12.0
8.0
8.0
8.0
8.0
8.0
16.0
16.0
16.0
12.0
12.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
SO
NS
PW
PW
D
TSSOP
TSSOP
SOIC
5.6
2500
2500
2000
10.3
10.3
5.6
SOIC
D
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CD74HC138M96
CD74HC238M96
CD74HC238NSR
CD74HC238PWR
CD74HC238PWT
CD74HCT138M96
CD74HCT238M96
CD74HCT238PWR
SOIC
SOIC
D
D
16
16
16
16
16
16
16
16
2500
2500
2000
2000
250
333.2
333.2
367.0
367.0
367.0
333.2
333.2
367.0
345.9
345.9
367.0
367.0
367.0
345.9
345.9
367.0
28.6
28.6
38.0
35.0
35.0
28.6
28.6
35.0
SO
NS
PW
PW
D
TSSOP
TSSOP
SOIC
2500
2500
2000
SOIC
D
TSSOP
PW
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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相关型号：
CD74HC138SME4
IC HC/UH SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, SSOP-16, Decoder/Driver
TI
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