CD74HC153M [TI]
High Speed CMOS Logic Dual 4-Input Multiplexer; 高速CMOS逻辑双路4输入多路复用器
| 型号： | CD74HC153M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Dual 4-Input Multiplexer |
| 文件： | 总6页 (文件大小：43K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC153,
CD74HCT153
Data sheet acquired from Harris Semiconductor
SCHS151
High Speed CMOS Logic
Dual 4-Input Multiplexer
September 1997
Features
Description
• Common Select Inputs
• Separate Enable Inputs
• Buffered inputs and Outputs
The Harris CD74HC153 and CD74HCT153 are dual 4 to line
selector/multiplexers which select one of 4 to 1 line
selector/multiplexers which select one of four sources for
each section by the common select inputs, S0 and S1. When
the enable inputs (1E, 2E) are HIGH, the outputs are in the
LOW state.
[ /Title
(CD74H
C153,
CD74H
CT153)
/Subject
(High
Speed
CMOS
Logic
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
PKG.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
NO.
E16.3
E16.3
CD74HC153E
CD74HCT153E
CD74HC153M
CD74HCT153M
CD54HC153W
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld PDIP
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
Dual 4-
Input
16 Ld SOIC M16.15
16 Ld SOIC M16.15
Wafer
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30%of V
IL IH
at
CC
V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Pinout
CD74HC153, CD74HCT153
(PDIP, SOIC)
TOP VIEW
1E
S1
1
2
3
4
5
6
7
8
16 V
CC
15 2E
14 S0
1I
1I
1I
1I
3
2
1
0
13 2I
12 2I
11 2I
10 2I
3
2
1
0
1Y
9
2Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1774.1
Copyright © Harris Corporation 1997
1
CD74HC153, CD74HCT153
Functional Diagram
1
1E
6
5
1I
1I
1I
1I
0
1
2
3
7
SEL/MUX
1Y
4
3
14
2
S0
S1
10
11
12
13
15
2I
2I
2I
2I
0
1
2
3
9
SEL/MUX
2Y
GND = 8
= 16
2E
V
CC
TRUTH TABLE
DATA INPUTS
SELECT INPUTS
ENABLE OUTPUT
S1
S0
X
L
I0
X
L
I
I
I
3
E
H
L
L
L
L
L
L
L
L
Y
L
1
2
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
X
X
L
L
L
L
L
H
X
X
X
X
X
X
H
L
L
H
H
L
L
H
X
X
X
X
H
L
H
H
H
L
H
X
X
H
L
H
H
H
H
H
NOTE:
Select inputs S1 and S0 are common to both sections.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
2
CD74HC153, CD74HCT153
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD74HC153, CD74HCT153
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE: For dual-supply systems theorectical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
Data
UNIT LOADS
0.45
Enable
0.6
1.35
Select
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
HC TYPES
MIN TYP MAX MIN
MAX
MIN
MAX UNITS
Propagation Delay (Figure 1)
S to Y
t
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
160
32
-
-
-
-
-
-
-
-
-
200
40
-
-
-
-
-
-
-
-
-
240
48
-
ns
ns
ns
ns
ns
ns
ns
ns
PLH,
L
PHL
C =15pF
13
-
L
C = 50pF
6
27
145
29
-
34
180
36
-
41
220
44
-
L
I to Y
t
C = 50pF
2
-
PLH,
L
t
PHL
4.5
5
-
C =15pF
12
-
L
C = 50pF
6
25
31
38
L
4
CD74HC153, CD74HCT153
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
V
CC
(V)
PARAMETER
E to Y
MIN TYP MAX MIN
MAX
150
MIN
MAX UNITS
t
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
120
24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
180
36
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH,
L
PHL
30
-
C =15pF
9
-
L
C = 50pF
6
20
75
15
13
10
-
26
95
19
16
10
-
31
110
22
19
10
-
L
Output Transition Time
(Figure 1)
t
, t
C = 50pF
L
2
-
TLH THL
4.5
6
-
-
Input Capacitance
C
-
-
-
-
IN
Power Dissipation Capacitance
(Notes 4, 5)
C
5
45
PD
HCT TYPES
Propagation Delay (Figure 2)
S to Y
t
t
,
PLH
PHL
C = 50pF
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
14
-
34
-
-
-
-
-
-
-
-
-
-
-
-
43
-
-
-
-
-
-
-
-
-
-
-
51
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
L
C =15pF
L
I to Y
I to Y
E to Y
t
t
t
,
C = 50pF
4.5
5
24
-
30
-
36
-
PLH
L
t
PHL
C =15pF
9
L
,
C = 50pF
4.5
5
34
-
43
-
51
-
PLH
L
t
PHL
C =15pF
14
-
L
,
C = 50pF
4.5
5
27
-
34
41
-
PLH
L
t
PHL
C =15pF
11
-
L
Output Transition Time
Input Capacitance
t
, t
C = 50pF
L
4.5
-
15
10
-
19
10
-
22
10
-
TLH THL
C
-
-
-
IN
Power Dissipation Capacitance
(Notes 4, 5)
C
5
45
PD
NOTES:
4. C
is used to determine the dynamic power consumption, per multiplexer.
2
PD
5. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage.
D
CC
i
L
i
L
CC
Test Circuit and Waveform
t = 6ns
t = 6ns
f
r
E
90%
V
S
10%
I OR S
V
S
OUTPUT Y
t
t
PHL
PLH
FIGURE 1. PROPAGATION DELAY TIMES
5
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