CD74HC161 [TI]
High Speed CMOS Logic Presettable Counters; 高速CMOS逻辑可预置计数器
| 型号： | CD74HC161 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Presettable Counters |
| 文件： | 总10页 (文件大小：67K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC161, CD74HCT161,
CD74HC163, CD74HCT163
Data sheet acquired from Harris Semiconductor
SCHS154
High Speed CMOS Logic
Presettable Counters
February 1998
Features
Description
• CD74HC161, CD74HCT161 4-Bit Binary Counter,
Asynchronous Reset
The Harris CD74HC161, CD74HCT161, CD74HC163 and
CD74HCT163 are presettable synchronous counters that
feature look-ahead carry logic for use in high-speed
counting applications. The CD74HC161 and CD74HCT161
are asynchronous reset decade and binary counters,
respectively; the CD74HC163 and CD74HCT163 devices
decade and binary counters, respectively and are reset
synchronously with the clock. Counting and parallel
presetting are both accomplished synchronously with the
negative-to-positive transition of the clock.
[ /Title
(CD74
HC161
,
CD74
HCT16
1,
CD74
HC163
,
CD74
HCT16
3)
• CD74HC163, CD74HCT163 4-Bit Binary Counter,
Synchronous Reset
• Synchronous Counting and Loading
• Two Count Enable Inputs for n-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
A low level on the synchronous parallel enable input, SPE,
disables counting operation and allows data at the P0 to P3
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C inputs to be loaded into the counter (provided that the
setup and hold requirements for SPE are met).
• Balanced Propagation Delay and Transition Times
All counters are reset with a low level on the Master Reset
input, MR. In the CD74HC163 and CD74HCT163 counters
(synchronous reset types), the requirements for setup and
hold time with respect to the clock must be met.
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
/Sub-
ject
- 2V to 6V Operation
Two count enables, PE and TE, in each counter are
provided for n-bit cascading. In all counters reset action
occurs regardless of the level of the SPE, PE and TE inputs
(and the clock input, CP, in the CD74HC161 and
CD74HCT161 types).
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
(High
Speed
CMOS
Logic
Preset-
table
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
If a decade counter is preset to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
IL
IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Counte
rs)
/Autho
r ()
/Key-
words
(High
Speed
CMOS
Logic
Preset-
table
The look-ahead carry feature simplifies serial cascading of
the counters. Both count enable inputs (PE and TE) must
be high to count. The TE input is gated with the Q outputs
of all four stages so that at the maximum count the terminal
count (TC) output goes high for one clock period. This TC
pulse is used to enable the next cascaded stage.
Ordering Information
PKG.
NO.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
CD74HC161E
CD74HC161M
CD74HC163E
CD74HC163M
CD74HCT161E
CD74HCT161M
CD74HCT163E
CD74HCT163M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP
E16.3
16 Ld SOIC M16.15
16 Ld PDIP E16.3
16 Ld SOIC M16.15
16 Ld PDIP E16.3
16 Ld SOIC M16.15
16 Ld PDIP E16.3
16 Ld SOIC M16.15
Pinout
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
(PDIP, SOIC)
TOP VIEW
MR
CP
P0
1
2
3
4
5
6
7
8
16 V
CC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 TE
Counte
rs,
High
Speed
P1
P2
1. When ordering, use the entire part number. Add the suffix 96 to ob-
tain the variant in the tape and reel.
P3
PE
2. Wafer and die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or Harris
customer service for ordering information.
9
SPE
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1550.1
Copyright © Harris Corporation 1998
1
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Functional Diagram
P0 P1 P2 P3
3
4
5
6
9
2
14
13
12
11
15
SPE
CP
MR
PE
Q0
Q1
Q2
Q3
TC
1
7
10
TE
MODE SELECT - FUNCTION TABLE FOR CD74HC/HCT161
INPUTS
OUTPUTS
OPERATING MODE
Reset (Clear)
MR
L
CP
X
↑
PE
TE
SPE
P
Q
TC
L
n
n
X
X
X
X
L
Parallel Load
H
X
X
l
l
L
H
L
H
↑
X
X
l
h
X
X
X
(Note 3)
(Note 3)
(Note 3)
L
Count
Inhibit
H
↑
h
I (Note 4)
X
h
X
h (Note 5)
h (Note 5)
h (Note 5)
Count
H
X
X
q
q
n
n
H
I (Note 4)
MODE SELECT - FUNCTION TABLE FOR CD74HC/HCT163
INPUTS
OUTPUTS
OPERATING MODE
MR
CP
↑
PE
TE
SPE
P
Q
TC
n
n
Reset (Clear)
Parallel Load
l
X
X
X
X
l
L
L
h (Note 5)
h (Note 5)
h (Note 5)
h (Note 5)
h (Note 5)
↑
X
X
l
L
H
L
↑
X
X
l
h
X
X
X
(Note 3)
(Note 3)
(Note 3)
L
Count
Inhibit
↑
h
I (Note 4)
X
h
X
h (Note 5)
h (Note 5)
h (Note 5)
Count
X
X
q
q
n
n
I (Note 4)
NOTE: H = High voltage level steady state; L = Low voltage level steady state; h = High voltage level one setup time prior to the Low-to-High
clock transition; l = Low voltage level one setup time prior to the Low-to-High clock transition; X = Don’t Care; q = Lower case letters indicate
the state of the referenced output prior to the Low-to-High clock transition; ↑ = Low-to-High clock transition.
3. The TC output is High when TE is High and the counter is at Terminal Count (HHHH for CD74HC/HCT161 and CD74HC/HCT163).
4. The High-to-Low transition of PE or TE on the CD74HC/HCT161 and the CD74HC/HCT163 should only occur while CP is HIGH for con-
ventional operation.
5. The Low-to-High transition of SPE on the CD74HC/HCT161 and SPE or MR on the CD74HC/HCT163 should only occur while CP is HIGH
for conventional operation.
2
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 6)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
6. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
P0 - P3
0.25
PE
0.65
CP
1.05
MR
0.8
SPE
TE
0.5
1.05
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Maximum CP Frequency
(Note7)
f
-
2
6
-
-
-
-
-
-
5
-
-
-
4
-
-
-
MHz
MHz
MHz
MAX
4.5
6
30
35
24
28
20
24
4
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
CP Width (Low)
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
100
20
17
125
25
21
75
15
13
65
13
11
75
15
13
80
16
14
3
MAX
MIN
120
24
20
150
30
26
90
18
15
75
15
13
90
18
15
100
20
17
3
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
W(L)
-
-
-
-
-
-
-
-
-
-
2
4.5
6
80
16
14
100
20
17
60
12
10
50
10
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MR Pulse Width (161)
t
2
W
4.5
6
Setup Time, Pn to CP
t
t
t
t
2
SU
SU
SU
SU
4.5
6
Setup Time, PE or TE to CP
Setup Time, SPE to CP
Setup Time, MR to CP (163)
Hold Time, PN to CP
2
4.5
6
2
60
12
10
65
13
11
3
4.5
6
2
4.5
6
t
t
t
2
H
H
H
4.5
6
3
3
3
3
3
3
Hold Time, TE or PE to CP
Hold Time, SPE to CP
2
0
0
0
4.5
6
0
0
0
0
0
0
2
0
0
0
4.5
6
0
0
0
0
0
0
Recovery Time, MR to CP (161)
t
2
75
15
13
95
19
16
110
22
19
REC
4.5
6
HCT TYPES
Maximum CP Frequency
f
t
-
-
-
-
-
-
-
-
-
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
30
16
20
10
13
12
13
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
24
20
25
13
16
15
16
5
-
-
-
-
-
-
-
-
-
20
24
30
15
20
18
20
5
-
-
-
-
-
-
-
-
-
MHz
ns
MAX
CP Width (Low) (Note 7)
MR Pulse Width (161)
W(L)
t
ns
W
Setup Time, Pn to CP
t
t
t
t
ns
SU
SU
SU
SU
Setup Time, PE or TE to CP
Setup Time, SPE to CP
Setup Time, MR to CP (163)
Hold Time, PN to CP
ns
ns
ns
t
ns
H
H
Hold Time, TE or PE to CP
t
3
3
3
ns
5
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
Hold Time, SPE to CP
Recovery Time, MR to CP (161)
NOTE:
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
3
MAX
MIN
3
MAX
UNITS
ns
t
-
-
4.5
4.5
3
-
-
-
-
-
-
-
-
H
t
15
19
22
ns
REC
7. Applies to non-cascaded operation only. With cascaded counters clock to terminal count propagation delays, count enables (PE or TE)-
to-clock setup times, and count enables (PE or TE)-to-clock hold times determine maximum clock frequency. For example with these HC
devices:
1
1
----------------------------
37 + 10 + 0
f
(CP) = ----------------------------------------------------------------------------------------------------------------------------------------------------- =
CP-to-TC prop. delay + TE-to-CP setup + TE-to-CP Hold
≈ 21MHz(min)
MAX
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
CP to TC
t
, t
C
= 50pF
PHL PLH
L
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
185
37
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
230
46
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
280
56
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
C
C
C
= 15pF
= 50pF
= 50pF
15
-
L
L
L
6
31
185
37
-
39
230
46
-
48
280
56
-
CP to Qn
t
t
t
2
-
PHL, PLH
4.5
5
-
C
C
C
= 15pF
= 50pF
= 50pF
15
-
L
L
L
6
31
120
24
-
39
150
30
-
48
180
36
-
TE to TC
t
2
-
PHL, PLH
4.5
5
-
C
C
C
= 15pF
= 50pF
= 50pF
9
-
L
L
L
6
20
210
42
-
26
265
53
-
31
315
63
-
MR to Qn (161)
t
t
2
-
PHL
4.5
5
-
C
C
C
= 15pF
= 50pF
= 50pF
18
-
L
L
L
6
36
210
42
36
75
15
13
-
45
265
53
45
95
19
16
-
54
315
63
54
110
22
19
-
MR to TC (161)
2
-
PHL
4.5
6
-
C
C
= 50pF
= 50pF
-
L
Output Transition Time
t
, t
THL TLH
2
-
L
4.5
6
-
-
Power Dissipation Capacitance
(Notes 8, 9)
C
-
5
60
PD
6
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
Input Capacitance
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
10
MIN
MAX UNITS
CC
C
C
= 50pF
-
10
-
10
-
-
10
pF
IN
L
HCT TYPES
Propagation Delay
CP to TC
t
t
t
t
C
C
C
C
C
C
C
C
C
C
= 50pF
= 15pF
= 50pF
= 15pF
= 50pF
= 15pF
= 50pF
= 15pF
= 50pF
= 50pF
-
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
18
-
42
-
-
-
-
-
-
-
-
-
-
-
-
53
-
-
-
-
-
-
-
-
-
-
-
-
63
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
PHL, PLH
L
L
L
L
L
L
L
L
L
L
CP to Qn
t
4.5
5
39
-
49
-
59
-
PHL, PLH
16
-
TE to TC
t
4.5
5
32
-
40
-
48
-
PHL, PLH
13
-
MR to Qn (161)
t
t
4.5
5
50
-
63
-
75
-
PHL
PHL
21
-
MR to TC (161)
4.5
4.5
5
50
15
-
63
19
-
75
22
-
Output Transition Time
t
, t
THL TLH
-
Power Dissipation Capacitance
(Notes 6, 7)
C
63
PD
Input Capacitance
NOTES:
C
C
= 50pF
-
10
-
10
-
10
-
10
pF
IN
L
8. C
is used to determine the dynamic power consumption, per package.
PD
2
2
9. P = C
V
f + ∑(C V
f ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply
D
PD CC
i
L
CC
O
i
O
L
CC
Voltage.
7
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Timing Diagram
MASTER RESET (161)
(ASYNCHRONOUS)
(SYNCHRONOUS)
MASTER RESET (163)
SPE
P0
PRESET
DATA
INPUTS
P1
P2
P3
CP (161)
CP (163)
PE
COUNT
ENABLES
TE
Q0
Q1
Q2
OUTPUTS
Q3
TC
12
13
14
15
0
1
2
COUNT
INHIBIT
RESET PRESET
Sequence illustrated on waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit.
8
CD74HC161, CD74HCT161, CD74HC163, CD74HCT163
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
9
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