CD74HC173M96 [TI]
High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State; 高速CMOS逻辑四路D型触发器,三态型号: | CD74HC173M96 |
厂家: | TEXAS INSTRUMENTS |
描述: | High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State |
文件: | 总17页 (文件大小:372K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD54HC173, CD74HC173,
CD54HCT173, CD74HCT173
Data sheet acquired from Harris Semiconductor
SCHS158E
High-Speed CMOS Logic
Quad D-Type Flip-Flop, Three-State
February 1998 - Revised October 2003
Features
Description
The ’HC173 and ’HCT173 high speed three-state quad D-
type flip-flops are fabricated with silicon gate CMOS technol-
ogy. They possess the low power consumption of standard
CMOS Integrated circuits, and can operate at speeds com-
• Three-State Buffered Outputs
• Gated Input and Output Enables
• Fanout (Over Temperature Range)
[ /Title
(CD74H
C173,
CD74H
CT173)
/Subject
(High
Speed
CMOS
Logic
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads parable to the equivalent low power Schottky devices. The
buffered outputs can drive 15 LSTTL loads. The large output
drive capability and three-state feature make these parts ide-
ally suited for interfacing with bus lines in bus oriented sys-
tems.
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
The four D-type flip-flops operate synchronously from a com-
mon clock. The outputs are in the three-state mode when
either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their
present states without having to disrupt the clock If either of
the 2 input ENABLES are taken to a logic “1” level, the Q
outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Reset is enabled by taking the
MASTER RESET (MR) input to a logic “1” level. The data
outputs change state on the positive going edge of the clock.
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
at V
= 5V
CC
Quad D-
Type
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
The ’HCT173 logic family is functionally, as well as pin com-
patible with the standard LS logic family.
Ordering Information
Pinout
CD54HC173, CD54HCT173
(CERDIP)
CD74HC173
(PDIP, SOIC, SOP, TSSOP)
CD74HCT173
TEMP. RANGE
o
PART NUMBER
CD54HC173F3A
CD54HCT173F3A
CD74HC173E
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
(PDIP, SOIC)
TOP VIEW
OE
1
2
3
4
5
6
7
8
16 V
CC
CD74HC173M
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
15 MR
14 D0
13 D1
12 D2
11 D3
10 E2
OE2
CD74HC173MT
CD74HC173M96
CD74HC173NSR
CD74HC173PW
CD74HC173PWR
CD74HC173PWT
CD74HCT173E
CD74HCT173M
CD74HCT173MT
CD74HCT173M96
Q
Q
Q
Q
0
1
2
3
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
CP
9
E1
GND
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Functional Diagram
E1
E2
10
9
14
13
12
11
7
3
D0
D1
D2
D3
CP
Q
Q
Q
Q
0
1
2
3
4
5
6
15
1
2
MR
OE1
OE2
TRUTH TABLE
INPUTS
DATA ENABLE
DATA
OUTPUT
MR
H
L
CP
X
L
E1
X
X
H
X
L
E2
X
X
X
H
L
D
X
X
X
X
L
Q
n
L
Q
Q
Q
0
0
0
L
↑
L
↑
L
↑
L
L
↑
L
L
H
H
H= High Voltage Level
L = Low Voltage Level
X= Irrelevant
↑= Transition from Low to High Level
Q = Level Before the Indicated Steady-State Input Conditions Were
0
Established
NOTE:
1. When either OE1 or OE2 (or both) is (are) high, the output is dis-
abled to the high-impedance state, however, sequential opera-
tion of the flip-flops is not affected.
2
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Logic Diagram
9
E1
10
E2
V
CC
D
Q
Q
14
P
D0
3
Q
0
7
CP
CP
N
R
15
MR
1
OE1
2
OE2
13
D1
4
5
6
Q
Q
Q
1
2
3
12
3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT
IN DASHED ENCLOSURE
D2
11
D3
3
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Package Thermal Impedance, θ (see Note 2):
JA
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108 C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
CC
DC Input Diode Current, I
For V < -0.5V or V > V
o
IK
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
ο
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
o
o
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
o
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±70mA
CC
CC
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-6
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-7.8
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
7.8
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
8
80
160
CC
CC
GND
4
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Three-State Leakage
Current
I
V
V
or
IL
-
6
-
-
±0.5
-
±0.5
-
±10
µA
OZ
IH
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
6
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 3)
V
4.5 to
5.5
100
360
450
CC
-2.1
Three-State Leakage
Current
I
V
V
or
IL
-
5.5
-
-
±0.5
-
±5.0
-
±10
µA
OZ
IH
NOTE:
3. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
D0-D3
UNIT LOADS
0.15
0.15
0.25
0.2
E1 and E2
CP
MR
OE1 and OE2
0.5
NOTE: Unit Load is ∆I
CC
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
5
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
CONDITIONS
PARAMETER
HC TYPES
SYMBOL
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay, Clock to
Output
t
, t
C = 50pF
2
-
-
200
40
-
250
50
-
300
60
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
pF
pF
PLH PHL
L
4.5
C = 15pF
L
5
6
2
17
-
CL = 50pF
34
175
35
-
43
220
44
-
51
265
53
-
Propagation Delay, MR to
Output
t
C = 50pF
-
PHL
L
4.5
5
-
C = 15pF
L
12
-
CL = 50pF
CL = 50pF
6
30
150
30
-
37
190
38
-
45
225
45
-
Propagation Delay Output
Enable to Q (Figure 6)
t
t
, t
PLZ PHZ
2
, t
PZL PZH
C = 50pF
4.5
5
L
C = 15pF
L
12
CL = 50pF
6
26
60
12
10
-
33
75
15
13
-
38
90
18
15
-
Output Transition Times
t
, t
TLH THL
C = 50pF
2
-
-
L
4.5
6
-
Maximum Clock Frequency
Input Capacitance
f
C = 15pF
L
5
60
-
MAX
C
-
-
-
10
10
10
10
10
10
IN
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
29
-
-
-
pF
PD
(Notes 4, 5)
HCT TYPES
Propagation Delay, Clock to
Output
t
, t
PLH PHL
C = 50pF
4.5
5
-
40
-
50
-
60
-
ns
ns
L
C = 15pF
17
-
L
Propagation Delay, MR to
Output
t
C = 50pF
4.5
5
44
-
55
-
66
-
ns
PHL
L
C = 15pF
L
18
ns
Propagation Delay Output
Enable to Q (Figure 6)
t , t
PZL PZH
CL = 50pF
2
150
30
-
190
38
-
225
45
-
ns
C = 50pF
4.5
5
ns
L
C = 15pF
L
14
ns
CL = 50pF
6
26
15
-
33
19
-
38
22
-
ns
Output Transition Times
Maximum Clock Frequency
Input Capacitance
t
, t
TLH THL
C = 50pF
4.5
5
-
ns
L
f
C = 15pF
L
60
-
MHz
pF
pF
MAX
C
-
-
-
10
-
10
-
10
-
IN
Power Dissipation
Capacitance
C
5
34
PD
(Notes 4, 5)
NOTES:
4. C
is used to determine the dynamic power consumption, per package.
PD
5. P = V
2
2
f + ∑ (C V
+ f ) where f = Input Frequency, f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage.
CC
D
CC
i
L
CC
O
i
O
L
6
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL
V
(V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Maximum Clock Frequency
f
2
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
24
28
100
20
17
100
20
17
75
15
13
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
20
24
120
24
20
120
24
20
90
18
15
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
ns
MAX
4.5
30
35
80
16
14
80
16
14
60
12
10
3
6
2
MR Pulse Width
t
t
w
w
4.5
6
ns
ns
Clock Pulse Width
2
ns
4.5
6
ns
ns
Set-up Time, Data to Clock
and E to Clock
t
2
ns
SU
4.5
6
ns
ns
Hold Time, Data to Clock
Hold Time, E to Clock
t
t
2
ns
H
H
4.5
6
3
3
3
ns
3
3
3
ns
2
0
0
0
ns
4.5
6
0
0
0
ns
0
0
0
ns
Removal Time, MR to Clock
t
2
60
12
10
75
15
13
90
18
15
ns
REM
4.5
6
ns
ns
HCT TYPES
Maximum Clock Frequency
f
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
20
15
25
12
18
0
-
-
-
-
-
-
-
-
16
19
31
15
23
0
-
-
-
-
-
-
-
-
13
22
38
18
27
0
-
-
-
-
-
-
-
-
MHz
ns
MAX
MR Pulse Width
t
t
w
w
Clock Pulse Width
ns
Set-up Time, E to Clock
Set-up Time, Data to Clock
Hold Time, Data to Clock
Hold Time, E to Clock
Removal Time, MR to Clock
t
t
ns
SU
SU
ns
t
ns
H
H
t
0
0
0
ns
t
12
15
18
ns
REM
7
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
f
t C
f
L
CL
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
8
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Test Circuits and Waveforms (Continued)
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
9
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
CDIP
CDIP
PDIP
Drawing
5962-8682501EA
5962-8875901EA
CD54HC173F
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
16
16
16
1
1
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
J
1
CD54HC173F3A
CD54HCT173F3A
CD74HC173E
J
1
J
1
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC173M
CD74HC173M96
CD74HC173MT
CD74HC173NSR
CD74HC173PW
CD74HC173PWR
CD74HC173PWT
CD74HCT173E
CD74HCT173M
CD74HCT173M96
CD74HCT173MT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SO
D
D
16
16
16
16
16
16
16
16
16
16
16
40
2500
250
2000
90
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
D
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
NS
PW
PW
PW
N
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
TSSOP
TSSOP
TSSOP
PDIP
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-NC-NC-NC
2000
250
25
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
SOIC
SOIC
SOIC
D
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
D
2500
250
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
D
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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