CD74HC175M [TI]
High Speed CMOS Logic Quad D-Type Flip-Flop with Reset; 高速CMOS逻辑四路D型触发器与复位
| 型号： | CD74HC175M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Quad D-Type Flip-Flop with Reset |
| 文件： | 总7页 (文件大小：57K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC175,
CD74HCT175
Data sheet acquired from Harris Semiconductor
SCHS160
High Speed CMOS Logic
August 1997
Quad D-Type Flip-Flop with Reset
Features
Description
• Common Clock and Asynchronous Reset on Four
D-Type Flip-Flops
The Harris CD74HC175 and CD74HCT175 are high speed
Quad D-type Flip-Flops with individual D-inputs and Q, Q
complementary outputs. The devices are fabricated using
silicon gate CMOS technology. They have the low power
consumption advantage of standard CMOS ICs and the
ability to drive 10 LSTTL devices.
[ /Title
(CD74
HC175
,
• Positive Edge Pulse Triggering
• Complementary Outputs
• Buffered Inputs
Information at the D input is transferred to the Q, Q outputs on
the positive going edge of the clock pulse. All four Flip-Flops
are controlled by a common clock (CP) and a common reset
(MR). Resetting is accomplished by a low voltage level
independent of the clock. All four Q outputs are reset to a
logic 0 and all four Q outputs to a logic 1.
CD74
HCT17
5)
/Sub-
ject
(High
Speed
CMOS
Logic
Quad
D-
• Typical f
MAX
= 50MHz at V = 5V, C = 15pF,
CC L
o
T = 25 C
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
TEMP. RANGE
PKG.
NO.
o
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
CD74HC175E
CD74HCT175E
CD74HC175M
CD74HCT175M
CD74HCT175W
NOTES:
( C)
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
Wafer
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E16.3
• HC Types
- 2V to 6V Operation
E16.3
Type
Flip-
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
M16.15
M16.15
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL
IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
l
OL OH
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74HC175, CD74HCT175
(PDIP, SOIC)
TOP VIEW
MR
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q
Q
0
3
3
3
2
Q
D
D
Q
Q
Q
0
0
1
1
1
D
D
Q
Q
2
2
CP
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1474.1
Copyright © Harris Corporation 1997
1
CD74HC175, CD74HCT175
Functional Diagram
4
2
D
D
0
Q
Q
Q
Q
0
0
9
1
CP
CP
R
3
MR
5
12
13
7
6
D
1
D
Q
Q
Q
Q
1
1
CP
R
10
11
D
2
D
Q
Q
Q
Q
2
2
CP
R
15
14
D
3
D
Q
Q
Q
Q
3
3
CP
R
TRUTH TABLE
INPUTS
OUTPUTS
RESET (MR)
CLOCK CP
DATA D
Q
Q
n
n
n
L
H
H
H
X
↑
X
H
L
L
H
H
L
L
↑
H
L
X
Q
Q
0
0
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level,
Q = Level Before the Indicated Steady-State Input Conditions Were Established.
0
Logic Diagram
C
C
ONE OF FOUR F/F
L
L
L
4 (5, 12, 13)
D
D
3( 6, 11, 14)
p
n
p
n
n
Q
n
C
L
C
L
C
C
L
p
n
p
n
C
C
L
L
C
C
2( 7, 10, 15)
L
L
Q
n
R
CP
1
9
8
16
MR
CP
TO OTHER THREE F/F
TO OTHER THREE F/F
GND
V
CC
2
CD74HC175, CD74HCT175
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
110
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO +85 C -55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
V
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
8
80
160
CC
CC
GND
3
CD74HC175, CD74HCT175
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO +85 C -55 C TO 125 C
PARAMETER
HCT TYPES
SYMBOL V (V)
I
(mA)
V (V) MIN TYP MAX
CC
MIN
MAX
MIN
MAX
UNITS
I
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTES:
4. For dual-supply systems theorectical worst case (V = 2.4V, V
= 5.5V) specification is 1.8mA.
CC
I
5. Die for this part number is available which meets all electrical specifications.
HCT Input Loading Table
INPUT
UNIT LOADS
MR
1
CP
D
0.60
0.15
NOTE: Unit Load is ∆I
Specifications table, e.g. 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Clock Pulse Width
t
t
-
-
2
80
16
14
80
16
14
-
-
-
-
-
-
-
-
-
-
-
-
100
20
-
-
-
-
-
-
120
24
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
w
4.5
6
17
20
MR Pulse Width
2
100
20
120
24
w
4.5
6
17
20
4
CD74HC175, CD74HCT175
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
100
20
17
5
MAX
MIN
120
24
20
5
MAX
UNITS
ns
Setup Time, Data to Clock
t
-
-
-
-
2
4.5
6
80
16
14
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SU
ns
ns
Hold Time, Data to Clock
Removal Time, MR to Clock
Clock Frequency
t
2
ns
H
4.5
6
5
5
5
ns
5
5
5
ns
t
2
5
5
5
ns
REM
4.5
6
5
5
5
ns
5
5
5
ns
f
2
6
5
4
MHz
MHz
MHz
MAX
4.5
6
30
35
25
29
20
23
HCT TYPES
Clock Pulse Width
t
t
-
-
-
-
-
-
4.5
4.5
4.5
4.5
4.5
4.5
20
20
20
5
-
-
-
-
-
-
-
-
-
-
-
-
25
25
25
5
-
-
-
-
-
-
30
30
30
5
-
-
-
-
-
-
ns
ns
w
MR Pulse Width
w
Setup Time Data to Clock
Hold Time Data to Clock
Removal Time MR to Clock
Clock Frequency
t
ns
SU
t
ns
H
t
5
5
5
ns
REM
f
25
20
16
MHz
MAX
Switching Specifications Input t , t = 6ns
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay, Clock to
Q or Q
t
, t
PLH PHL
C = 50pF
2
4.5
6
-
-
175
35
30
-
220
44
37
-
265
53
45
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
L
-
C = 15pF
5
14
-
L
Propagation Delay,
MR to Q or Q
t , t
PLH PHL
C = 50pF
2
175
35
30
-
220
44
37
-
265
53
45
-
L
4.5
6
-
-
C = 15pF
5
14
-
L
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
75
15
13
10
-
95
19
16
10
-
110
22
19
10
-
4.5
6
-
-
C
-
-
-
-
IN
Power Dissipation
Capacitance
C
5
65
PD
(Notes 6, 7)
5
CD74HC175, CD74HCT175
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
HCT TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay,
Clock to Q or Q
t
, t
PLH PHL
C = 50pF
4.5
-
13
-
33
-
41
-
50
-
ns
ns
ns
ns
ns
pF
pF
L
C = 15pF
5
L
Propagation Delay,
MR to Q or Q
t , t
PLH PHL
C = 50pF
4.5
5
35
-
44
-
53
-
L
C = 15pF
17
-
L
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
15
10
-
19
10
-
22
10
-
C
-
-
-
IN
Power Dissipation
Capacitance
C
5
67
PD
(Notes 6, 7)
NOTES:
6. C
is used to determine the dynamic power consumption, per flip-flop.
PD
7. P = V
2
2
f + ∑ (C V
+ f ) where f = Input Frequency, f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
CC
O
i
O
L
Test Circuits and Waveforms
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
1.3V
90%
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
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