CD74HC21M96 [TI]
High-Speed CMOS Logic Dual 4-Input AND Gate; 高速CMOS逻辑双路4输入与门型号: | CD74HC21M96 |
厂家: | TEXAS INSTRUMENTS |
描述: | High-Speed CMOS Logic Dual 4-Input AND Gate |
文件: | 总10页 (文件大小:265K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD54HC21, CD74HC21,
CD74HCT21
Data sheet acquired from Harris Semiconductor
SCHS131C
High-Speed CMOS Logic
Dual 4-Input AND Gate
August 1997 - Revised September 2003
Features
Description
• Buffered Inputs
The ’HC21 and CD74HCT21 logic gates utilize silicon gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integrated circuits. All devices have the ability to drive
10 LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.
• Typical Propagation Delay: 9ns at V
o
= 5V,
[ /Title
(CD74H
C21,
CD74H
CT21)
/Subject
(High
Speed
CMOS
Logic
Dual 4-
Input
CC
C = 15pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
TEMP. RANGE
o
PART NUMBER
CD54HC21F3A
CD74HC21E
( C)
PACKAGE
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
• Significant Power Reduction Compared to LSTTL
Logic ICs
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HC Types
- 2V to 6V Operation
CD74HC21M
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
CD74HC21MT
CD74HC21M96
CD74HCT21E
CD74HCT21M
CD74HCT21MT
CD74HCT21M96
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC21
(CERDIP)
CD74HC21, CD74HCT21
(PDIP, SOIC)
TOP VIEW
1A
1B
1
2
3
4
5
6
7
14 V
CC
13 2D
12 2C
11 NC
10 2B
NC
1C
1D
1Y
9
8
2A
2Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC21, CD74HC21, CD74HCT21
Functional Diagram
1
1A
2
1B
6
1Y
4
1C
5
1D
9
2A
10
2B
8
2Y
12
2C
GND = 7
13
V
= 14
CC
2D
NC = 3, 11
TRUTH TABLE
INPUTS
OUTPUT
nA
L
nB
X
nC
X
nD
X
nY
L
X
L
X
X
L
X
X
L
X
L
X
X
X
L
L
H
H
H
H
H
H = High Voltage Level, L = Low Voltage Level, X = Irrelevant
Logic Symbol
nA
nB
nY
nC
nD
2
CD54HC21, CD74HC21, CD74HCT21
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
80
86
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
4.5
3.15
-
-
3.15
-
-
3.15
6
2
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
1.9
1.9
OH
IH
V
IL
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
IH
V
IL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD54HC21, CD74HC21, CD74HCT21
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Quiescent Device
Current
I
V
GND
or
0
6
-
-
2
-
20
-
40
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
5.5
5.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
Low Level Output
Voltage
CMOS Loads
V
V
or
IH
0.02
4
-
-
-
0.1
-
-
-
0.1
0.33
±1
-
-
-
0.1
0.4
±1
OL
V
IL
Low Level Output
Voltage
TTL Loads
0.26
±0.1
V
Input Leakage
Current
I
V
0
µA
I
CC
and
GND
Quiescent Device
Current
I
V
or
0
-
-
-
-
2
-
-
20
-
-
40
µA
µA
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
490
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All
UNIT LOADS
1
NOTE: Unit Load is ∆I
Specifications table, e.g. 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Propagation Delay, Input to
Output (Figure 1)
t
, t
PLH PHL
C = 50pF
2
4.5
6
-
-
-
-
-
-
110
22
19
-
-
-
-
-
140
28
24
-
-
-
-
-
165
33
28
-
ns
ns
ns
ns
L
-
Propagation Delay, Data Input to
Output Y
t , t
PLH PHL
C = 15pF
5
9
L
4
CD54HC21, CD74HC21, CD74HCT21
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
95
19
16
10
-
MIN
MAX
110
22
UNITS
ns
Transition Times (Figure 1)
t
, t
TLH THL
C = 50pF
L
2
4.5
6
-
-
-
-
-
-
-
75
15
13
10
-
-
-
-
-
-
-
-
-
-
-
ns
-
19
ns
Input Capacitance
C
-
-
-
-
10
pF
I
Power Dissipation Capacitance
(Notes 3, 4)
C
5
36
-
pF
PD
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
t
, t
C = 50pF
4.5
5
-
-
-
27
-
-
-
34
-
-
-
41
-
ns
ns
RHL PHL
L
Propagation Delay, Data Input to
Output Y
t
, t
C = 15pF
11
PLH PHL
L
Transition Times (Figure 2)
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
-
-
-
-
-
15
10
-
-
-
-
19
10
-
-
-
-
22
10
-
ns
pF
pF
C
-
-
I
Power Dissipation Capacitance
(Notes 3, 4)
C
5
42
PD
NOTES:
3. C
is used to determine the dynamic power consumption, per gate.
2
PD
4. P = V
f (C
PD
+ C ) where f = input frequency, C = output load capacitance, V = supply voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
PDIP
Drawing
CD54HC21F3A
CD74HC21E
ACTIVE
ACTIVE
J
14
14
1
None
Call TI
Level-NC-NC-NC
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC21M
CD74HC21M96
CD74HC21MT
CD74HCT21E
CD74HCT21M
CD74HCT21M96
CD74HCT21MT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
D
D
D
N
D
D
D
14
14
14
14
14
14
14
50
2500
250
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
2500
250
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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