CD74HC243MTE4 [TI]
High-Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs; 高速CMOS逻辑四路总线收发器,具有三态输出型号: | CD74HC243MTE4 |
厂家: | TEXAS INSTRUMENTS |
描述: | High-Speed CMOS Logic Quad-Bus Transceiver with Three-State Outputs |
文件: | 总14页 (文件大小:444K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD54HC243, CD74HC243,
CD54HCT243, CD74HCT243
Data sheet acquired from Harris Semiconductor
SCHS168D
High-Speed CMOS Logic
Quad-Bus Transceiver with Three-State Outputs
November 1997 - Revised October 2003
Features
Description
• Typical Propagation Delay (A to B, B to A) of 7ns at
The ’HC243 and ’HCT243 silicon-gate CMOS three-state
bidirectional noninverting buffers are intended for two-way
asynchronous communication between data buses. They
have high-drive-current outputs that enable high-speed oper-
ation when driving large bus capacitances. These circuits
possess the low power dissipation of CMOS circuits and
have speeds comparable to low-power Schottky TTL circuits.
o
V
= 5V, C = 15pF, T = 25 C
CC
L A
[ /Title
(CD74
HCT24
2,
CD74
HC243
,
CD74
HCT24
3)
/Sub-
ject
(High
Speed
CMOS
Logic
Quad-
• Three-State Outputs
• Buffered Inputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads They can drive 15 LSTTL loads.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
The states of the output-enable (OEB, OEA) inputs
determine both the direction of flow (A to B, B to A), and the
three-state mode.
• Significant Power Reduction Compared to LSTTL
Logic ICs
Ordering Information
• HC Types
- 2V to 6V Operation
TEMP. RANGE
o
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
PART NUMBER
CD54HC243F3A
CD54HCT243F3A
CD74HC243E
( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
at V
= 5V
CC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
CD74HC243M
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
CD74HC243MT
CD74HC243M96
CD74HCT243E
CD74HCT243M
Pinout
CD54HC243, CD54HCT243
(CERDIP)
CD74HC243, CD74HCT243
(PDIP, SOIC)
14 Ld SOIC
TOP VIEW
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
OEB
NC
A0
1
2
3
4
5
6
7
14 V
CC
13 OEA
12 NC
11 B0
A1
A2
10 B1
A3
9
8
B2
B3
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD54HC243, CD74HC243, CD54HCT243, CD74HCT243
Functional Diagram
‘HC243, ‘HCT243
3
11
10
9
A0
A1
A2
A3
B0
B1
B2
B3
4
5
6
8
1
OEB
OEA
DIRECTION
SELECT LOGIC
13
TRUTH TABLE
HC, HCT243 SERIES
DATA PORT STATUS
CONTROL INPUTS
OEB
OEA
An
Bn
I
H
L
H
H
L
O
Z
Z
I
Z
H
L
Z
L
O
H= High Voltage Level
L= Low Voltage Level
I= Input
O= Output (Same Level as Input)
Z= High Impedance
To prevent excess currents in the High Z modes all I/O terminals should be terminated with 10kΩ
to 1MΩ resistors.
2
CD54HC243, CD74HC243, CD54HCT243, CD74HCT243
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
CC
DC Input Diode Current, I
For V < -0.5V or V > V
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±70mA
CC
CC
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-6
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-7.8
Low Level Output
Voltage
CMOS Loads
V
V
V
or
0.02
0.02
0.02
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
7.8
3
CD54HC243, CD74HC243, CD54HCT243, CD74HCT243
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
Input Leakage
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
I
V
or
-
6
-
-
-
-
-
-
±0.1
-
±1
-
±1
µA
I
CC
GND
Current
Quiescent Device
Current
I
V
or
0
-
6
6
8
-
-
80
-
-
160
µA
µA
CC
CC
GND
Three-State Leakage
Current
I
V
or
IL
±0.5
±0.5
±10
OZ
V
IH
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
6
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
-
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
Three-State Leakage
Current
I
V
V
or
IL
-
5.5
-
-
±0.5
-
±5.0
-
±10
µA
OZ
IH
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
An, Bn
UNIT LOADS
1.1
0.6
OEA, OEB
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
CC
4
CD54HC243, CD74HC243, CD54HCT243, CD74HCT243
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
CONDITIONS
PARAMETER
HC TYPES
SYMBOL
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay Data
to Outputs
t
, t
C = 50pF
2
-
-
90
18
-
115
23
-
135
27
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
L
4.5
C = 15pF
L
5
6
2
7
-
CL = 50pF
15
150
30
-
20
190
38
-
23
225
45
-
Output High-Z, to High Level
to Low Level
t
t
C = 50pF
L
-
PZL, PZH
CL = 50pF
CL = 15pF
CL = 50pF
4.5
5
-
12
-
6
26
150
30
-
33
190
38
-
38
225
45
-
Output High Level,
Output Low Level to High-Z
t
t
C = 50pF
L
2
-
PHZ, PLZ
CL = 50pF
CL = 15pF
CL = 50pF
4.5
5
-
12
-
6
26
60
12
10
10
20
33
75
15
13
10
20
38
90
18
15
10
20
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
-
4.5
6
-
-
C
-
-
-
-
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
80
-
-
-
pF
PD
(Notes 3, 4)
HCT TYPES
Propagation Delay Data to
Outputs
t
, t
C = 50pF
4.5
5
-
9
-
22
-
28
-
33
-
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH PHL
L
C = 15pF
L
Output High-Z to High Level
to Low Level
t
, t
C = 50pF
4.5
5
34
-
43
-
51
-
PZH PZL
L
C = 15pF
14
-
L
Output High Level,
Output Low Level to High-Z
t
, t
PHZ PLZ
C = 50pF
4.5
5
35
-
44
-
53
-
L
C = 15pF
14
-
L
Output Transition Times
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
12
10
20
15
10
20
18
10
20
C
-
-
-
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
91
-
-
-
pF
PD
(Notes 3, 4)
NOTES:
3. C
is used to determine the dynamic power consumption, per channel.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply Voltage.
D
CC
i
L
i
O
L
CC
5
CD54HC243, CD74HC243, CD54HCT243, CD74HCT243
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC AND HCT TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
6
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
CDIP
PDIP
Drawing
8409001CA
CD54HC243F
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
14
14
14
14
14
1
1
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
CD54HC243F3A
CD54HCT243F3A
CD74HC243E
J
1
J
1
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC243EE4
CD74HC243M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
N
D
D
D
D
D
D
D
D
D
N
N
D
D
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC243M96
CD74HC243M96E4
CD74HC243M96G4
CD74HC243ME4
CD74HC243MG4
CD74HC243MT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC243MTE4
CD74HC243MTG4
CD74HCT243E
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT243EE4
CD74HCT243M
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT243ME4
CD74HCT243MG4
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CD74HC243M96
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 14
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
CD74HC243M96
D
2500
Pack Materials-Page 2
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