概述
数据手册
替代型号CD74HC273 概述
High Speed CMOS Logic Octal D-Type Flip-Flop with Reset 高速CMOS逻辑八路D类触发器与复位
CD74HC273 数据手册
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PDF下载CD74HC273,
CD74HCT273
Data sheet acquired from Harris Semiconductor
SCHS174
High Speed CMOS Logic
February 1998
Octal D-Type Flip-Flop with Reset
Features
Description
• Common Clock and Asynchronous Master Reset
• Positive Edge Triggering
• Buffered Inputs
The Harris CD74HC273 and CD74HCT273 high speed octal
D-Type flip-flops with a direct clear input are manufactured
with silicon-gate CMOS technology. They possess the low
power consumption of standard CMOS integrated circuits.
[ /Title
(CD74
HC273
,
CD74
HCT27
3)
Information at the D inputis transferred to the Q outputs on
the positive-going edge of the clock pulse. All eight flip-flops
are controlled by a common clock (CP) and a common reset
(MR). Resetting is accomplished by a low voltage level
independent of the clock. All eight Q outputs are reset to a
logic 0.
• Typical f
MAX
= 60MHz at V = 5V, C = 15pF,
CC L
o
T = 25 C
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
/Sub-
ject
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
TEMP. RANGE
PKG.
NO.
(High
Speed
CMOS
Logic
Octal
D-
o
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
CD54HC273F
CD54HCT273F
CD74HC273E
CD74HCT273E
CD74HC273M
CD74HCT273M
NOTES:
( C)
PACKAGE
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
20 Ld CERDIP F20.3
20 Ld CERDIP F20.3
• HC Types
- 2V to 6V Operation
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
E20.3
E20.3
M20.3
M20.3
- High Noise Immunity: N = 30%, N = 30% of V
CC
IL
IH
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
Type
Flip-
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD54HC273, CD54HCT273, CD74HC273, CD74HCT273
(PDIP, SOIC, CERDIP)
TOP VIEW
1
2
3
4
5
6
7
8
9
V
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
20
19
CC
Q7
18 D7
17 D6
16 Q6
15
14
Q5
D5
13 D4
12
Q4
11 CP
GND 10
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1479.2
Copyright © Harris Corporation 1998
1
CD74HC273, CD74HCT273
Functional Diagram
CLOCK
CP
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
DATA
INPUTS
DATA
OUTPUTS
RESET MR
TRUTH TABLE
INPUTS
OUTPUT
RESET (MR)
CLOCK CP
DATA D
Q
L
n
L
H
H
H
X
↑
X
H
L
H
L
↑
L
X
Q
0
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low
to High Level, Q = Level Before the Indicated Steady-State Input Conditions Were Established.
0
2
CD74HC273, CD74HCT273
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
PDIP Package . . . . . . . . . . . . . . . . . . .
CERDIP Package . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
JC
125
105
120
N/A
44
N/A
IK
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
O
O
CC
o
o
DC Drain Current, per Output, I
O
o
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
DC Output Source or Sink Current per Output Pin, I
(SOIC - Lead Tips Only)
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-4
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-5.2
Low Level Output
Voltage
CMOS Loads
V
or
0.02
0.02
0.02
4
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
V
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
5.2
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
8
80
160
CC
CC
GND
3
CD74HC273, CD74HCT273
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HCT TYPES
SYMBOL V (V)
I
(mA)
V (V) MIN TYP MAX
CC
MIN
MAX
MIN
MAX
UNITS
I
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
IH
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
V
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
UNIT LOADS
MR
1.5
0.4
1.5
Data
CP
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Prerequisite For Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
Maximum Clock Frequency
(Figure 1)
f
-
-
2
6
-
-
-
-
-
-
-
-
-
-
-
-
5
-
-
-
-
-
-
4
-
-
-
-
-
-
MHz
MHz
MHz
ns
MAX
4.5
6
30
35
60
12
10
25
29
75
15
13
20
23
90
18
15
MR Pulse Width
(Figure 1)
t
2
W
4.5
6
ns
ns
4
CD74HC273, CD74HCT273
Prerequisite For Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
SYMBOL CONDITIONS (V)
MIN TYP MAX
MIN
100
20
17
75
15
13
3
MAX
MIN
120
24
20
70
18
15
3
MAX
UNITS
ns
Clock Pulse Width (Figure 1)
t
-
-
-
-
2
4.5
6
80
16
14
60
12
10
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
W
ns
ns
Set-up Time Data to Clock
(Figure 5)
t
2
ns
SU
4.5
6
ns
ns
Hold Time, Data to Clock
(Figure 5)
t
2
ns
H
4.5
6
3
3
3
ns
3
3
3
ns
Removal Time, MR to Clock
t
2
50
10
9
65
13
11
75
15
13
ns
REM
4.5
6
ns
ns
HCT TYPES
Maximum Clock Frequency
(Figure 2)
f
-
-
4.5
4.5
25
12
-
-
-
-
20
15
-
-
16
18
-
-
MHz
ns
MAX
MR Pulse Width
(Figure 2)
t
w
w
Clock Pulse Width (Figure 2)
t
-
-
4.5
4.5
20
12
-
-
-
-
25
15
-
-
30
18
-
-
ns
ns
Set-up Time Data to Clock
(Figure 6)
t
SU
Hold Time, Data to Clock
(Figure 6)
t
-
-
4.5
4.5
3
-
-
-
-
3
-
-
3
-
-
ns
ns
H
Removal Time, MR to Clock
t
10
13
15
REM
Switching Specifications Input t , t = 6ns
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
HC TYPES
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Propagation Delay,
Clock to Output
(Figure 3)
t
, t
C = 50pF
2
4.5
6
-
-
150
30
26
-
190
38
30
-
225
45
38
-
ns
ns
PLH PHL
L
-
ns
C = 15pF
5
12
-
ns
L
Propagation Delay,
MR to Output
(Figure 3)
t
C = 50pF
2
150
30
26
75
15
13
10
-
190
38
30
95
19
16
10
-
225
45
38
110
22
19
10
-
ns
PHL
L
4.5
6
-
ns
-
ns
Output Transition Time
(Figure 3)
t
, t
TLH THL
C = 50pF
L
2
-
ns
4.5
6
-
ns
-
ns
Input Capacitance
C
-
-
-
pF
MHz
I
Maximum Clock Frequency
f
C = 15pF
5
60
MAX
L
5
CD74HC273, CD74HCT273
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
PARAMETER
SYMBOL
CONDITIONS
V
(V)
TYP
MAX
MAX
MAX
UNITS
CC
Power Dissipation
Capacitance
C
-
5
25
-
-
-
pF
PD
(Notes 5, 6)
HCT TYPES
Propagation Delay,
Clock to Output (Figure 4)
t
, t
PLH PHL
C = 50pF
4.5
-
12
-
30
-
38
-
45
-
ns
ns
ns
L
C = 15pF
5
L
Propagation Delay,
t
C = 50pF
4.5
32
40
48
PHL
L
MR to Output (Figure 4)
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
-
15
10
-
19
10
-
22
10
-
ns
pF
C
-
-
IN
Maximum Clock Frequency
f
C = 15pF
L
5
50
25
MHz
pF
MAX
Power Dissipation
Capacitance
C
-
5
-
-
-
PD
(Notes 5, 6)
NOTES:
5. C
is used to determine the dynamic power consumption, per flip-flop.
PD
6. P = C
2
2
V
f + ∑ (C V
+ f ) where f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply
D
PD CC
i
L
CC
O
i
O
L
CC
Voltage.
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%.
accordance with device truth table. For f
, input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
CD74HC273, CD74HCT273
Test Circuits and Waveforms (Continued)
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
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CD74HC273 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| CD54HC273 | TI | High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset | 功能相似 |
|
CD74HC273 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CD74HC273E | TI | High Speed CMOS Logic Octal D-Type Flip-Flop with Reset | 获取价格 |
|
| CD74HC273EE4 | TI | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20, ROHS COMPLIANT, PLASTIC, DIP-20 | 获取价格 |
|
| CD74HC273EN | ETC | Logic IC | 获取价格 |
|
| CD74HC273EX | RENESAS | IC,FLIP-FLOP,OCTAL,D TYPE,HC-CMOS,DIP,20PIN,PLASTIC | 获取价格 |
|
| CD74HC273F | ETC | Logic IC | 获取价格 |
|
| CD74HC273H | ETC | Octal D-Type Flip-Flop | 获取价格 |
|
| CD74HC273M | TI | High Speed CMOS Logic Octal D-Type Flip-Flop with Reset | 获取价格 |
|
| CD74HC273M96 | TI | High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset | 获取价格 |
|
| CD74HC273M96E4 | TI | 具有复位功能的高速 CMOS 逻辑八路 D 型触发器 | DW | 20 | -55 to 125 | 获取价格 |
|
| CD74HC273M96G4 | TI | High Speed CMOS Logic Octal D-Type Flip-Flops with Reset 20-SOIC -55 to 125 | 获取价格 |
|
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