CD74HC365E [TI]
High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting; 高速CMOS逻辑六角缓冲器/线路驱动器，三态非反相和反相
| 型号： | CD74HC365E |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting |
| 文件： | 总8页 (文件大小：51K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC365, CD74HCT365,
CD74HC366, CD74HCT366
Data sheet acquired from Harris Semiconductor
SCHS180
High Speed CMOS Logic Hex Buffer/Line Driver,
Three-State Non-Inverting and Inverting
November 1997
Features
Description
• Buffered Inputs
The Harris CD74HC365, CD74HCT365, CD74HC366, and
CD74HCT366 silicon gate CMOS three-state buffers are
general purpose high-speed non-inverting and inverting
• High Current Bus Driver Outputs
[ /Title
(CD74
HC365
,
CD74
HCT36
5,
buffers. They have high drive current outputs which enable
high speed operation even when driving large bus
capacitances. These circuits possess the low power
dissipation of CMOS circuitry, yet have speeds comparable to
low power Schottky TTL circuits. Both circuits are capable of
• Typical Propagation Delay t
, t
= 8ns at V = 5V,
CC
PLH PHL
o
C = 15pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads driving up to 15 low power Schottky inputs.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C The CD74HC365 and CD74HCT365 are non-inverting buffers,
whereas the CD74HC366 and CD74HCT366 are inverting
buffers. These devices have two three-state control inputs (OE1
and OE2) which are NORed together to control all six gates.
CD74
HC366
,
CD74
HCT36
6)
/Sub-
ject
(High
Speed
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
The CD74HCT365 and CD74HCT366 logic families are speed,
function and pin compatible with the standard 74LS logic family.
• HC Types
- 2V to 6V Operation
Ordering Information
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
TEMP. RANGE
PKG.
NO.
at V
= 5V
CC
o
PART NUMBER
CD74HC365E
CD74HCT365E
CD74HC366E
CD74HC365M
CD74HCT365M
NOTES:
( C)
PACKAGE
16 Ld PDIP
16 Ld PDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
• HCT Types
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E16.3
- 4.5V to 5.5V Operation
E16.3
- Direct LSTTL Input Logic Compatibility,
E16.3
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
M16.15
M16.15
l
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD74HC365, CD74HCT365, CD74HC366, CD74HCT366
(PDIP, SOIC)
TOP VIEW
OE1
1A
1
2
3
4
5
6
7
8
16 V
CC
15 OE2
14 6A
(1Y) 1Y
2A
13 6Y (6Y)
12 5A
(2Y) 2Y
3A
11 5Y (5Y)
10 4A
(3Y) 3Y
GND
9
4Y (4Y)
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1539.1
Copyright © Harris Corporation 1997
1
CD74HC365, CD74HCT365, CD74HC366, CD74HCT366
Functional Diagrams
CD74HC365, CD75HCT365
CD74HC366, CD75HCT366
1
16
1
16
OE1
1A
V
CC
OE1
1A
V
CC
2
3
15
14
2
3
15
14
OE2
6A
OE2
6A
1Y
1Y
4
13
12
4
13
12
2A
6Y
5A
5Y
4A
4Y
2A
6Y
5A
5Y
4A
4Y
5
6
5
6
2Y
2Y
11
10
11
10
3A
3A
7
8
7
8
3Y
3Y
9
9
GND
GND
TRUTH TABLE
OUTPUTS
(Y)
INPUTS
OE1
OE2
L
A
HC/HCT365
HC/HCT366
L
L
H
X
X
L
H
Z
Z
H
L
L
X
L
H
Z
Ζ
H
X
NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance (OFF) State
2
CD74HC365, CD74HCT365, CD74HC366, CD74HCT366
Logic Diagram
V
CC
16
ONE OF SIX IDENTICAL CIRCUITS
2
1A
3
(NOTE)
1Y
GND
8
1
OE1
OE2
4
5
2A
15
2Y
6
7
9
3A
3Y
4Y
5Y
6Y
10
4A
12
11
5A
14
6A
13
NOTE: Inverter not included in HC/HCT365.
FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT365 AND HC/HCT366 (OUTPUTS FOR HC/HCT365 ARE COMPLEMENTS OF
THOSE SHOWN, i.e., 1Y, 2Y, ETC.)
3
CD74HC365, CD74HCT365, CD74HC366, CD74HCT366
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
115
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
HC TYPES
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
High Level Input
Voltage
V
-
-
-
2
1.5
3.15
4.2
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
3.15
4.2
-
-
1.5
3.15
4.2
-
-
V
V
V
V
V
V
V
V
V
V
V
IH
4.5
-
-
-
6
2
-
-
-
Low Level Input
Voltage
V
-
0.5
0.5
0.5
IL
4.5
6
-
1.35
-
1.35
-
1.35
-
1.8
-
1.8
-
1.8
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
2
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
OH
IH
V
IL
-0.02
-0.02
-6
4.5
6
High Level Output
Voltage
TTL Loads
4.5
6
-7.8
Low Level Output
Voltage
CMOS Loads
V
or
0.02
0.02
0.02
6
2
4.5
6
-
-
-
-
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
V
V
V
V
V
OL
IH
V
IL
0.1
0.1
Low Level Output
Voltage
TTL Loads
4.5
6
0.26
0.26
0.33
0.33
7.8
Input Leakage
Current
I
V
or
-
6
6
-
-
-
-
±0.1
-
-
±1
-
-
±1
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
0
8
80
160
CC
CC
GND
4
CD74HC365, CD74HCT365, CD74HC366, CD74HCT366
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL V (V)
I
(mA)
V
(V) MIN TYP MAX
MIN
MAX
MIN
MAX
UNITS
I
O
CC
Three-State Leakage
Current
I
V
V
or
V
=
or
6
-
-
±0.5
-
±5.0
-
±10
µA
OZ
IL
O
V
IH
CC
GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
V
IL
High Level Output
Voltage
TTL Loads
-4
0.02
4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IH
V
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
to
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
V
4.5 to
5.5
100
360
450
CC
CC
-2.1
Three-State Leakage
Current
I
V
V
or
V
=
or
5.5
-
-
±0.5
-
±5.0
-
±10
µA
OZ
IL
O
V
IH
CC
GND
NOTE:
4. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
OE1
UNIT LOADS
0.6
All Others
0.55
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25 C.
limit specified in DC Electrical
o
CC
Switching Specifications - HC/HCT365 Input t , t = 6ns
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
MAX
TEST
CONDITIONS
PARAMETER
HC TYPES
SYMBOL
V
(V)
TYP
MAX
MAX
UNITS
CC
Propagation Delay,
Data to Outputs
HC/HCT365
t
, t
C = 50pF
2
-
-
105
21
18
-
130
26
22
-
160
32
27
-
ns
ns
ns
ns
PLH PHL
L
4.5
6
5
-
C = 15pF
8
L
5
CD74HC365, CD74HCT365, CD74HC366, CD74HCT366
Switching Specifications - HC/HCT365 Input t , t = 6ns (Continued)
r
f
o
-55 C TO
125 C
o
o
o
o
25 C
-40 C TO 85 C
TEST
CONDITIONS
PARAMETER
SYMBOL
V
(V)
TYP
MAX
110
22
19
-
MAX
140
28
24
-
MAX
165
33
28
-
UNITS
ns
CC
Propagation Delay,
Data to Outputs
HC/HCT366
t , t
PLH PHL
C = 50pF
2
-
-
L
4.5
ns
6
5
2
-
ns
C = 15pF
9
-
ns
L
Propagation Delay,
Output Enable and Disable
to Outputs
t , t
PLH PHL
C = 50pF
150
30
26
-
190
38
33
-
225
45
38
-
ns
L
4.5
6
-
ns
-
ns
C = 15pF
5
12
-
ns
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
2
60
12
10
10
20
75
15
13
10
20
90
18
15
10
20
ns
4.5
6
-
ns
-
ns
C
-
-
-
-
pF
pF
I
Three-State Output
Capacitance
C
-
-
O
Power Dissipation
Capacitance
C
-
5
40
-
-
-
pF
PD
(Notes 5, 6)
HCT TYPES
Propagation Delay,
Data to Outputs
HC/HCT365
t
t
t
, t
C = 50pF
4.5
5
-
25
-
31
-
38
-
ns
ns
PLH PHL
L
C = 15pF
9
L
Propagation Delay,
Data to Outputs
HC/HCT366
, t
PLH PHL
C = 50pF
4.5
5
-
27
-
34
-
41
-
ns
ns
L
C = 15pF
11
L
Propagation Delay,
Output Enable and Disable
to Outputs
, t
PLH PHL
C = 50pF
4.5
5
-
35
-
44
-
53
-
ns
ns
L
C = 15pF
14
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
L
4.5
-
-
12
10
20
-
15
10
20
-
18
10
20
-
ns
pF
pF
pF
C
-
-
-
-
-
IN
Three-State Capacitance
C
-
O
Power Dissipation
Capacitance
C
5
42
PD
(Notes 5, 6)
NOTES:
5. C
PD
is used to determine the dynamic power consumption, per buffer.
2
6. P = V
CC
f (C
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
i
PD
L
i
L
6
CD74HC365, CD74HCT365, CD74HC366, CD74HCT366
Test Circuits and Waveforms
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 3. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 4. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 5. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
PLZ
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
V
, C = 50pF.
CC
L
FIGURE 6. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
7
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