CD74HC390EE4 [TI]
High-Speed CMOS Logic Dual Decade Ripple Counter; 高速CMOS逻辑双路十年纹波计数器
| 型号： | CD74HC390EE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Dual Decade Ripple Counter |
| 文件： | 总11页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC390,
CD54HCT390, CD74HCT390
Data sheet acquired from Harris Semiconductor
SCHS185C
High-Speed CMOS Logic
September 1997 - Revised October 2003
Dual Decade Ripple Counter
Features
Description
• Two BCD Decade or Bi-Quinary Counters
The CD74HC390 and ’HCT390 dual 4-bit decade ripple
counters are high-speed silicon-gate CMOS devices and are
pin compatible with low-power Schottky TTL (LSTTL). These
devices are divided into four separately clocked sections.
The counters have two divide-by-2 sections and two divide-
by-5 sections. These sections are normally used in a BCD
decade or bi-quinary configuration, since they share a com-
mon master reset (nMR). If the two master reset inputs (1MR
and 2MR) are used to simultaneously clear all 8 bits of the
counter, a number of counting configurations are possible
within one package. The separate clock inputs (nCP0 and
nCP1) of each section allow ripple counter or frequency divi-
sion applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100.
Each section is triggered by the High-to-Low transition of the
input pulses (nCP0 and nCP1).
• One Package Can Be Configured to Divide-by-2, 4,
5,10, 20, 25, 50 or 100
[ /Title
(CD74
HC390
,
CD74
HCT39
0)
/Sub-
ject
(High
Speed
CMOS
• Two Master Reset Inputs to Clear Each Decade
Counter Individually
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
For BCD decade operation, the nQ0 output is connected to
the nCP1 input of the divide-by-5 section. For bi-quinary
decade operation, the nO3 output is connected to the nCP0
• HC Types
- 2V to 6V Operation
input and nQ becomes the decade output.
0
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
The master reset inputs (1MR and 2MR) are active-High
asynchronous inputs to each decade counter which oper-
ates on the portion of the counter identified by the “1” and “2”
prefixes in the pin configuration. A High level on the nMR
input overrides the clock and sets the four outputs Low.
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
Ordering Information
l
OL OH
TEMP. RANGE
o
PART NUMBER
CD54HCT390F3A
CD74HC390E
( C)
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
Pinout
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
CD54HCT390
(CERDIP)
CD74HC390, CD74HCT390
(PDIP, SOIC)
CD74HC390M
TOP VIEW
CD74HC390MT
CD74HC390M96
CD74HCT390E
CD74HCT390M
CD74HCT390MT
CD74HCT390M96
1CP0
1MR
1
2
3
4
5
6
7
8
16 V
CC
15 2CP0
14 2MR
13 2Q0
1Q
0
1CP1
1Q
1Q
1Q
12 2CP1
1
2
3
11 2Q
10 2Q
1
2
3
9
2Q
GND
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
CD74HC390, CD54HCT390, CD74HCT390
Functional Diagram
1 (15)
2 (14)
3 (13)
nCP0
nMR
nQ
0
÷
2
COUNTER
5 (11)
nQ
nQ
nQ
1
2
6 (10)
7 (9)
÷
5
4 (12)
COUNTER
nCP1
3
GND = 8
V
= 16
CC
TRUTH TABLE
INPUTS
CP
↑
MR
ACTION
No Change
Count
L
L
↓
X
H
All Qs Low
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
B-QUINARY COUNT SEQUENCE FOR 1/2 THE 390
OUTPUTS
BCD COUNT SEQUENCE FOR 1/2 THE 390
OUTPUTS
COUNT
Q0
L
Q1
L
Q2
L
Q3
L
COUNT
Q0
L
Q1
L
Q2
L
Q3
L
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
L
H
L
L
L
H
L
L
L
L
L
H
H
L
L
H
H
L
L
L
L
H
L
L
H
L
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
H
L
L
H
L
L
L
H
L
H
H
H
L
L
H
H
L
L
L
H
L
L
H
L
L
H
H
H
H
L
L
Output nQ3 connected to nCP0 with counter input on nCP1.
Output nQ0 connected to nCP1 with counter input on nCP0.
2
CD74HC390, CD54HCT390, CD74HCT390
Logic Diagram
4(12)
nCP1
Q
Q
Q
Q
1(15)
nCP0
Φ
Φ
Φ
Φ
R
R
R
R
2(14)
nMR
V
= 16
CC
GND = 8
3(13)
0
5(11)
1
6(10)
2
7(9)
3
nQ
nQ
nQ
nQ
3
CD74HC390, CD54HCT390, CD74HCT390
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
67
73
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
4
CD74HC390, CD54HCT390, CD74HCT390
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
nCP0
UNIT LOADS
0.45
0.6
nCP1, MR
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.,
CC
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
CHARACTERISTIC
HC TYPES
SYMBOL
V
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
CC
Maximum Clock
Frequency
f
2
6
-
-
-
-
-
-
-
-
-
-
-
-
5
24
28
100
20
17
-
-
-
-
-
-
4
20
24
120
24
20
-
-
-
-
-
-
MHz
MHz
MHz
ns
MAX
4.5
30
35
80
16
14
6
2
Clock Pulse Width,
nCP0, nCP1
t
W
4.5
6
ns
ns
5
CD74HC390, CD54HCT390, CD74HCT390
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
CHARACTERISTIC
SYMBOL
t
V
(V)
MIN
70
14
12
50
10
9
TYP
MAX
MIN
90
18
15
65
13
11
MAX
MIN
105
21
MAX
UNITS
ns
CC
Reset Removal Time
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
REM
4.5
ns
6
2
18
ns
Reset Pulse Width
t
75
ns
W
4.5
6
15
ns
13
ns
HCT TYPES
Maximum Clock
Frequency
f
MAX
4.5
4.5
27
19
-
-
-
-
22
24
-
-
18
29
-
-
MHz
ns
Clock Pulse Width,
nCP0, nCP1
t
W
Reset Removal Time
Reset Pulse Width
t
4.5
4.5
15
13
-
-
-
-
19
16
-
-
22
20
-
-
ns
ns
REM
t
W
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
PARAMETER
HC TYPES
Propagation Delay (Figure 1)
SYMBOL CONDITIONS
(V)
MIN TYP MAX
MIN
MAX
MIN
MAX UNITS
t
C = 50pF
2
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
175
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
220
44
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
265
53
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PLH,
L
t
PHL
nCP0 to nQ
nCP1 to nQ
nCP1 to nQ
nCP1 to nQ
0
1
2
3
C =15pF
14
-
L
C = 50pF
6
30
185
37
31
245
49
42
180
36
-
37
230
46
39
305
61
52
225
45
-
45
280
56
48
370
74
63
270
54
-
L
t
t
t
C = 50pF
2
-
PLH,
L
t
PHL
4.5
6
-
-
C = 50pF
2
-
PLH,
L
t
PHL
4.5
6
-
-
C = 50pF
2
-
PLH,
L
t
PHL
4.5
5
-
15
-
6
31
365
73
62
190
38
-
38
455
91
77
240
48
-
46
550
110
94
285
57
-
nCP0 to nQ3
(nQ connected to nCP1)
t
t
C = 50pF
2
-
PLH,
L
t
0
PHL
4.5
6
-
-
MR to Q
C = 50pF
2
-
n
PLH,
L
t
PHL
4.5
5
-
C =15pF
16
-
L
C = 50pF
6
32
41
48
L
6
CD74HC390, CD54HCT390, CD74HCT390
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
TEST
V
CC
(V)
PARAMETER
SYMBOL CONDITIONS
MIN TYP MAX
MIN
MAX
95
19
16
10
-
MIN
MAX UNITS
Output Transition Time
(Figure 1)
t
, t
C = 50pF
2
4.5
6
-
-
-
-
-
-
-
75
15
13
10
-
-
-
-
-
-
-
-
-
-
-
110
22
19
10
-
ns
ns
ns
pF
pF
TLH THL
L
-
Input Capacitance
C
C = 50pF
-
-
IN
L
Power Dissipation Capacitance
(Notes 3, 4)
C
C =15pF
5
28
PD
L
HCT TYPES
Propagation Delay (Figure 1)
t
t
C = 50pF
4.5
5
-
-
-
-
17
-
40
-
-
-
-
50
-
-
-
-
60
-
ns
ns
ns
PLH,
L
PHL
nCP0 to nQ
nCP1 to nQ
C =15pF
L
0
t
t
t
C = 50pF
4.5
43
51
65
1
PLH,
L
t
PHL
nCP1 to nQ
nCP1 to nQ
C = 50pF
4.5
4.5
-
-
-
-
55
42
-
-
69
53
-
-
83
63
ns
ns
2
PLH,
L
t
PHL
C = 50pF
3
PLH,
L
t
PHL
C =15pF
5
-
-
18
-
-
-
-
-
-
-
-
ns
ns
L
nCP0 to nQ2
(nQ connected to nCP1)
t
t
C = 50pF
4.5
84
105
126
PLH,
L
t
0
PHL
MR to Q
C = 50pF
4.5
5
-
-
-
-
-
-
18
-
42
-
-
-
-
-
-
53
-
-
-
-
-
-
63
-
ns
ns
ns
pF
pF
n
PLH,
L
t
PHL
C =15pF
L
Output Transition
Input Capacitance
t
, t
C = 50pF
4.5
-
15
10
-
19
10
-
22
10
-
TLH THL
L
C
C =15pF
-
IN
L
Power Dissipation Capacitance
(Notes 3, 4)
C
C =15pF
5
32
PD
L
NOTES:
3. C
is used to determine the dynamic power consumption, per multiplexer.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
7
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
相关型号：
CD74HC390M
Decade Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 3-Bit, Up Direction, CMOS, PDSO16,
ROCHESTER
©2020 ICPDF网 联系我们和版权申明