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CD74HC4002MTG4 [TI]

High-Speed CMOS Logic Dual 4-Input NOR Gate; 高速CMOS逻辑双路4输入或非门
CD74HC4002MTG4
型号： CD74HC4002MTG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

High-Speed CMOS Logic Dual 4-Input NOR Gate
高速CMOS逻辑双路4输入或非门

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CD54HC4002, CD74HC4002  
Data sheet acquired from Harris Semiconductor  
SCHS197E  
High-Speed CMOS Logic  
Dual 4-Input NOR Gate  
August 1997 - Revised October 2003  
Features  
Description  
• Typical Propagation Delay = 8ns at V  
o
= 5V,  
The ’HC4002 logic gate utilizes silicon gate CMOS  
technology to achieve operating speeds similar to LSTTL  
gates with the low power consumption of standard CMOS  
integrated circuits. All devices have the ability to drive 10  
LSTTL loads. The ’HC4002 logic family is functional as well  
as pin compatible with the standard LS logic family.  
CC  
C = 15pF, T = 25 C  
L
A
[ /Title  
(CD74H  
C4002)  
/Subject  
(High  
Speed  
CMOS  
Logic  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
TEMP. RANGE  
o
PART NUMBER  
CD54HC4002F3A  
CD74HC4002E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld PDIP  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
Dual 4-  
Input  
NOR  
• HC Types  
- 2V to 6V Operation  
CD74HC4002M  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOP  
- High Noise Immunity: N = 30%, N = 30%of V  
IL IH  
at  
CC  
V
= 5V  
CD74HC4002MT  
CD74HC4002M96  
CD74HC4002NSR  
CD74HC4002PW  
CD74HC4002PWR  
CD74HC4002PWT  
CC  
Gate)  
14 Ld TSSOP  
14 Ld TSSOP  
14 Ld TSSOP  
NOTE: When ordering, use the entire part number. The suffixes 96  
and R denote tape and reel. The suffix T denotes a small-quantity  
reel of 250.  
Pinout  
CD54HC4002  
(CERDIP)  
CD74HC4002  
(PDIP, SOIC, SOP, TSSOP)  
TOP VIEW  
1Y  
1A  
1
2
3
4
5
6
7
14 V  
CC  
13 2Y  
12 2D  
11 2C  
10 2B  
1B  
1C  
1D  
NC  
GND  
9
8
2A  
NC  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
CD54HC4002, CD74HC4002  
Functional Diagram  
2
1A  
3
1B  
1
1Y  
4
1C  
5
1D  
9
2A  
10  
2B  
13  
2Y  
11  
12  
2C  
GND = 7  
V
= 14  
CC  
2D  
NC = 6, 8  
TRUTH TABLE  
INPUTS  
OUTPUT  
nA  
L
nB  
nC  
L
nD  
L
nY  
H
L
L
X
H
X
X
H
X
X
X
X
X
L
X
H
X
X
L
X
H
L
H = High Voltage Level, L = Low Voltage Level, X = Irrelevant  
Logic Symbol  
nA  
nB  
nY  
nC  
nD  
2
CD54HC4002, CD74HC4002  
Absolute Maximum Ratings  
Thermal Information  
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Package Thermal Impedance, θ (see Note 1):  
JA  
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 C/W  
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 C/W  
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 C/W  
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113 C/W  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
o
IK  
o
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
OK  
For V < -0.5V or V > V  
I
I
CC  
o
DC Output Diode Current, I  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
o
DC Output Source or Sink Current per Output Pin, I  
O
o
o
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
o
DC V  
or Ground Current, I  
I
. . . . . . . . . . . . . . . . . .±50mA  
CC  
CC or GND  
(SOIC - Lead Tips Only)  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. The package thermal impedance is calculated in accordance with JESD 51-7.  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
V
CC  
PARAMETER  
SYMBOL  
V (V)  
I
I
(mA)  
(V)  
MIN  
TYP  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
V
O
High Level Input  
Voltage  
V
-
-
2
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
IH  
4.5  
6
3.15  
-
-
3.15  
-
-
3.15  
V
4.2  
4.2  
4.2  
-
V
Low Level Input  
Voltage  
V
-
-
2
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
V
IL  
4.5  
6
-
-
-
V
-
-
-
V
High Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
-0.02  
2
1.9  
1.9  
1.9  
V
OH  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
V
5.9  
-
5.9  
-
5.9  
-
V
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
V
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
V
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
V
Low Level Output  
Voltage  
CMOS Loads  
V
V
or V  
IH IL  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
V
OL  
4.5  
6
V
V
Low Level Output  
Voltage  
TTL Loads  
-
V
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
V
5.2  
-
V
Input Leakage  
Current  
I
V
or  
6
µA  
I
CC  
GND  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
2
-
20  
-
40  
µA  
CC  
CC  
3
CD54HC4002, CD74HC4002  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
PARAMETER  
HC TYPES  
SYMBOL  
CONDITIONS  
V
(V)  
TYP  
MAX  
MAX  
MAX  
UNITS  
CC  
Propagation Delay,  
nA, nB, nC, nD to nY  
t
t
C = 50pF  
2
-
-
100  
20  
17  
-
125  
25  
21  
-
150  
30  
26  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
pF  
pF  
PLH, PHL  
L
4.5  
6
5
2
-
C = 15pF  
8
-
L
Output Transition Times  
(Figure 1)  
t
, t  
TLH THL  
C = 50pF  
L
75  
15  
13  
10  
-
95  
19  
16  
10  
-
110  
22  
19  
10  
-
4.5  
6
-
-
Input Capacitance  
C
-
-
-
IN  
Power Dissipation  
C
C = 15pF  
5
22  
PD  
L
Capacitance (Notes 2, 3)  
NOTES:  
2. C  
is used to determine the dynamic power consumption, per gate.  
2
PD  
3. P = V  
f (C  
PD  
+ C ) where f = Input Frequency, C = Output Load Capacitance, V  
= Supply Voltage.  
D
CC  
i
L
i
L
CC  
Test Circuit and Waveform  
t = 6ns  
t = 6ns  
f
r
V
CC  
90%  
50%  
10%  
INPUT  
GND  
t
t
TLH  
THL  
90%  
50%  
10%  
INVERTING  
OUTPUT  
t
t
PLH  
PHL  
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC  
4
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Copyright © 2007, Texas Instruments Incorporated  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
CDIP  
PDIP  
Drawing  
CD54HC4002F3A  
CD74HC4002E  
ACTIVE  
ACTIVE  
J
14  
14  
1
TBD  
A42 SNPB  
N / A for Pkg Type  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CD74HC4002EE4  
CD74HC4002M  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
PDIP  
SOIC  
N
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC4002M96  
CD74HC4002M96E4  
CD74HC4002M96G4  
CD74HC4002ME4  
CD74HC4002MG4  
CD74HC4002MT  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC4002MTE4  
CD74HC4002MTG4  
CD74HC4002NSR  
CD74HC4002NSRE4  
CD74HC4002NSRG4  
CD74HC4002PW  
SOIC  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
NS  
NS  
NS  
PW  
PW  
PW  
PW  
PW  
PW  
PW  
PW  
PW  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
CD74HC4002PWE4  
CD74HC4002PWG4  
CD74HC4002PWR  
CD74HC4002PWRE4  
CD74HC4002PWRG4  
CD74HC4002PWT  
CD74HC4002PWTE4  
CD74HC4002PWTG4  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
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for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
TAPE AND REEL BOX INFORMATION  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
(mm)  
16  
CD74HC4002M96  
CD74HC4002NSR  
CD74HC4002PWR  
D
14  
14  
14  
SITE 41  
SITE 41  
SITE 41  
6.5  
8.2  
7.0  
9.0  
10.5  
5.6  
2.1  
2.5  
1.6  
8
12  
8
16  
16  
12  
Q1  
Q1  
Q1  
NS  
PW  
330  
16  
330  
12  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
CD74HC4002M96  
CD74HC4002NSR  
CD74HC4002PWR  
D
14  
14  
14  
SITE 41  
SITE 41  
SITE 41  
346.0  
346.0  
346.0  
346.0  
346.0  
346.0  
33.0  
33.0  
29.0  
NS  
PW  
Pack Materials-Page 2  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°–8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  

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