CD74HC4052NSRG4 [TI]
High-Speed CMOS Logic Analog Multiplexers/Demultiplexers; 高速CMOS逻辑模拟多路复用器/多路解复用器
| 型号： | CD74HC4052NSRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Analog Multiplexers/Demultiplexers |
| 文件： | 总29页 (文件大小：643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54/74HC4051, CD54/74HCT4051,
CD54/74HC4052, CD74HCT4052,
CD54/74HC4053, CD74HCT4053
Data sheet acquired from Harris Semiconductor
SCHS122I
High-Speed CMOS Logic
November 1997 - Revised July 2004
Analog Multiplexers/Demultiplexers
Features
Ordering Information
TEMP. RANGE
o
• Wide Analog Input Voltage Range . . . . . . . . . .±5V Max
• Low “On” Resistance
PART NUMBER
CD74HC4051E
( C)
PACKAGE
16 Ld PDIP
[ /Title
(CD54
HC405
1,
CD74
HC405
1,
CD74
HCT40
51,
CD74
HC405
2,
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
- 70Ω Typical (V
- 40Ω Typical (V
- V = 4.5V)
EE
- V = 9V)
EE
CC
CC
CD74HC4051M
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
CD74HC4051MT
CD74HC4051M96
CD74HC4051NSR
CD74HC4051PWR
CD74HC4051PWT
CD74HC4052E
• Low Crosstalk between Switches
• Fast Switching and Propagation Speeds
• “Break-Before-Make” Switching
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
o
o
• Wide Operating Temperature Range . . -55 C to 125 C
• CD54HC/CD74HC Types
CD74HC4052M
- Operation Control Voltage . . . . . . . . . . . . . . 2V to 6V
- Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V
CD74HC4052MT
CD74HC4052M96
CD74HC4052NSR
CD74HC4052PW
CD74HC4052PWR
CD74HC4052PWT
CD74HC4053E
- High Noise Immunity . . . N = 30%, N = 30% of V
,
IL IH CC
V
= 5V
CC
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
• CD54HCT/CD74HCT Types
- Operation Control Voltage . . . . . . . . . . . 4.5V to 5.5V
- Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V
- Direct LSTTL Input
Logic Compatibility . . . V = 0.8V Max, V = 2V Min
CD74HC4053M
IL
IH
- CMOS Input Compatibility. . . . . I ≤ 1µA at V , V
OL OH
I
CD74HC4053MT
CD74HC4053M96
CD74HC4053NSR
CD74HC4053PW
CD74HC4053PWR
CD74HC4053PWT
CD74HCT4051E
CD74HCT4051M
CD74HCT4051MT
CD74HCT4051M96
CD74HCT4052E
CD74HCT4052M
CD74HCT4052MT
CD74HCT4052M96
CD74HCT4053E
CD74HCT4053M
CD74HCT4053MT
CD74HCT4053M96
CD74HCT4053PWR
CD74HCT4053PWT
Description
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld TSSOP
16 Ld TSSOP
These devices are digitally controlled analog switches which
utilize silicon gate CMOS technology to achieve operating
speeds similar to LSTTL with the low power consumption of
standard CMOS integrated circuits.
These analog multiplexers/demultiplexers control analog
voltages that may vary across the voltage supply range (i.e.
V
to V ). They are bidirectional switches thus allowing
CC
EE
any analog input to be used as an output and vice-versa.
The switches have low “on” resistance and low “off” leak-
ages. In addition, all three devices have an enable control
which, when high, disables all switches to their “off” state.
Ordering Information
TEMP. RANGE
o
PART NUMBER
CD54HC4051F3A
CD54HC4052F3A
CD54HC4053F3A
CD54HCT4051F3A
( C)
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
16 Ld CERDIP
-55 to 125
-55 to 125
-55 to 125
-55 to 125
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Pinouts
CD54HC4051, CD54HCT4051
(CERDIP)
CD54HC4052
(CERDIP)
CD74HC4051
CD74HC4052
(PDIP, SOIC, SOP, TSSOP)
CD74HCT4051
(PDIP, SOIC, SOP, TSSOP)
CD74HCT4052
(PDIP, SOIC)
(PDIP, SOIC)
TOP VIEW
TOP VIEW
A4
A6
A
1
2
3
4
5
6
7
8
16 V
CC
B0
B2
1
2
3
4
5
6
7
8
16 V
CC
CHANNEL
CHANNEL
IN/OUT
IN/OUT
15 A2
14 A1
13 A0
12 A3
11 S0
10 S1
15 A2
14 A1
CHANNEL
IN/OUT
COM OUT/IN
COM OUT/IN B
N
CHANNEL
IN/OUT
A7
A5
E
B3
B1
E
13 A
COM OUT/IN
CHANNEL
IN/OUT
N
CHANNEL
IN/OUT
12 A0
11 A3
10 S0
CHANNEL
IN/OUT
ADDRESS
SELECT
V
V
EE
EE
9
S2
GND
9
S1
GND
CD54HC4053
(CERDIP)
CD74HC4053
(PDIP, SOIC, SOP, TSSOP)
CD74HCT4053
(PDIP, SOIC, TSSOP)
TOP VIEW
B1
B0
C1
1
2
3
4
5
6
7
8
16 V
CC
CHANNEL
IN/OUT
15
B
COM OUT/IN
COM OUT/IN
N
14 A
N
COM OUT/IN C
13 A1
12 A0
11 S0
10 S1
N
CHANNEL
IN/OUT
IN/OUT C0
E
V
EE
9
S2
GND
2
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Functional Diagram of HC/HCT4051
CHANNEL IN/OUT
A
A
A
A
A
A
A
A
0
V
7
6
5
4
3
2
1
CC
16
4
2
5
1
12
15
14
13
TG
TG
TG
TG
TG
TG
TG
TG
S
11
10
9
0
S
S
1
2
A
BINARY
TO
1 OF 8
DECODER
WITH
ENABLE
COMMON
OUT/IN
3
LOGIC
LEVEL
CONVERSION
E
6
8
7
GND
V
EE
TRUTH TABLE
HC/HCT4051
INPUT STATES
“ON”
ENABLE
S
S
S
0
CHANNELS
2
1
L
L
L
L
L
L
L
L
H
L
L
L
A0
A1
L
L
L
H
H
L
H
L
A2
L
H
L
A3
H
H
H
H
X
A4
L
H
L
A5
H
H
X
A6
H
X
A7
None
X = Don’t care
3
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Functional Diagram of ’HC4052, CD74HCT4052
A CHANNELS IN/OUT
A
A
A
A
0
3
2
1
V
CC
11
15
14
12
16
TG
TG
TG
COMMON A
OUT/IN
BINARY
TO
1 OF 4
DECODER
WITH
ENABLE
TG
TG
13
3
LOGIC
LEVEL
CONVERSION
S
S
9
10
6
1
COMMON B
OUT/IN
0
TG
TG
TG
E
1
5
2
4
8
7
GND
V
B
B
B
B
3
EE
0
1
2
B CHANNELS IN/OUT
TRUTH TABLE
’HC4052, CD74HCT4052
INPUT STATES
“ON”
ENABLE
S
S
CHANNELS
1
0
L
L
L
A0, B0
A1, B1
A2. B2
A3, B3
None
L
L
H
H
X
H
L
L
L
H
X
H
X = Don’t care
4
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Functional Diagram of ’HC4053, CD74HCT4053
IN/OUT
BINARY TO
V
CC
1 OF 2
DECODERS
WITH ENABLE
C
C
B
B
A
A
0
1
0
1
0
1
LOGIC LEVEL
CONVERSION
16
3
5
1
2
13
12
TG
TG
TG
TG
TG
TG
A COMMON
OUT/IN
14
15
S
S
11
10
0
1
B COMMON
OUT/IN
S
9
6
2
C COMMON
OUT/IN
4
E
8
7
GND
V
EE
TRUTH TABLE
’HC4053, CD74HCT4053
INPUT STATES
“ON”
ENABLE
S
S
S
2
CHANNELS
C0, B0, A0
C0, B0, A1
C0, B1, A0
C0, B1, A1
C1, B0, A0
C1, B0, A1
C1, B1, A0
C1, B1, A1
None
0
1
L
L
L
L
L
H
L
L
H
H
L
L
L
L
L
H
L
L
L
H
H
H
H
X
L
H
L
L
L
H
H
X
L
H
X
H
X = Don’t care
5
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Absolute Maximum Ratings (Note 2)
Thermal Information
DC Supply Voltage, V
DC Supply Voltage, V
DC Supply Voltage, V
- V
EE
. . . . . . . . . . . . . . . . . -0.5V to 10.5V Package Thermal Impedance, θ (see Note 1):
JA
CC
o
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 C/W
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .108 C/W
CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.5V to -7V
o
o
DC Input Diode Current, I
IK
o
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
I
I
CC
o
DC Switch Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
OK
o
o
For V < V -0.5V or V > V
+ 0.5V . . . . . . . . . . . . . . . . .±20mA
+ 0.5V . . . . . . . . . . . . . . . . .±25mA
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
I
EE
I
CC
CC
o
DC Switch Current, (Note 2)
For V > V -0.5V or V < V
I
EE
I
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20mA
DC V Current, I
EE
EE
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
For maximum reliability, nominal operating conditions should be selected so that
operation is always within the following ranges
PARAMETER
MIN
MAX
UNITS
Supply Voltage Range (For T = Full Package Temperature Range), V
A
(Note 2)
CC
CD54/74HC Types
2
6
V
V
CD54/74HCT Types
4.5
5.5
Supply Voltage Range (For T = Full Package Temperature Range), V
A
- V
EE
CC
CD54/74HC Types, CD54/74HCT Types (See Figure 1)
2
10
V
Supply Voltage Range (For T = Full Package Temperature Range), V (Note 3)
A
EE
CD54/74HC Types, CD54/74HCT Types (See Figure 2)
0
-6
V
V
V
DC Input Control Voltage, V
GND
V
V
I
CC
CC
Analog Switch I/O Voltage, V
V
EE
IS
o
Operating Temperature, T
-55
125
C
A
Input Rise and Fall Times, t , t
r
f
2V
0
0
0
1000
500
ns
ns
ns
4.5V
6V
400
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. All voltages referenced to GND unless otherwise specified..
3. In certain applications, the external load resistor current may include both V
and signal line components. To avoid drawing V
current
CC
CC
when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6V (cal-
culated from r values shown in Electrical Specifications table). No V current will flow through R if the switch current flows into
ON
CC
L
terminal 3 on the HC/HCT4051; terminals 3 and 13 on the HC/HCT4052; terminals 4, 14 and 15 on the HC/HCT4053.
Recommended Operating Area as a Function of Supply Voltages
8
6
4
2
0
8
6
4
2
0
HCT
HCT
HC
HC
0
2
4
6
8
10 12
0
-2
-4
-6
-8
V
- V (V)
EE
V
EE
- GND (V)
CC
FIGURE 1.
FIGURE 2.
6
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
DC Electrical Specifications
TEST CONDITIONS
AMBIENT TEMPERATURE, T
A
o
o
o
o
o
25 C
-40 C - 85 C -55 C - 125 C
V
V
(V)
V
(V)
V
CC
(V)
IS
(V)
I
EE
PARAMETER
HC TYPES
High Level Input Voltage,
MIN
TYP
MAX
MIN
MAX
MIN
MAX UNITS
2
4.5
6
1.5
-
-
-
-
1.5
-
-
1.5
-
0
V
V
V
V
V
V
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
V
IH
3.15
3.15
3.15
4.2
-
-
4.2
-
4.2
-
Low Level Input Voltage,
2
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
160
140
120
180
160
130
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
200
175
150
225
200
162
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
240
210
180
270
240
195
-
V
IL
4.5
6
-
-
On Resistance, r
V
V
or V
V or
IL
0
0
4.5
6
70
60
40
90
80
45
10
8.5
5
ON
= 1mA, (Figure 11)
CC
CC
EE
I
V
O
IH
-4.5
0
4.5
4.5
6
to V
EE
0
-4.5
0
4.5
4.5
6
Maximum On Resistance
Between any Two
Channels, ∆r
ON
0
-
-
-
-4.5
4.5
-
-
-
Switch On/Off Leakage
Current, I
For Switch Off:
V
V
or
IL
When V = V
,
IZ
IS CC
IH
V
= V
;
OS
EE
1 and 2 Channels
4053
0
-5
0
6
5
6
5
6
5
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±0.1
±0.1
±0.1
±0.2
±0.2
±0.4
±0.1
-
-
-
-
-
-
-
±1
±1
±1
±2
±2
±4
±1
-
-
-
-
-
-
-
±1
±1
±1
±2
±2
±4
±1
µA
µA
µA
µA
µA
µA
µA
When V = V
,
EE
IS
= V
V
OS
CC
For Switch On:
All Applicable
Combinations of
4 Channels
4052
-5
0
V
and V
OS
IS
Voltage Levels
8 Channels
4051
-5
0
Control Input Leakage
Current, I
IL
V
or
CC
GND
Quiescent Device
Current, I
When V = V
IS
,
V
GND
or
0
6
5
-
-
-
-
8
-
-
80
-
-
160
320
µA
µA
EE
CC
V
= V
CC
OS
CC
I
= 0
O
When V = V
,
-5
16
160
IS
= V
CC
V
OS
EE
7
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
DC Electrical Specifications (Continued)
TEST CONDITIONS
AMBIENT TEMPERATURE, T
A
o
o
o
o
o
25 C
-40 C - 85 C -55 C - 125 C
V
V
(V)
V
(V)
V
CC
(V)
IS
(V)
I
EE
PARAMETER
HCT TYPES
High Level Input Voltage,
MIN
TYP
MAX
MIN
MAX
MIN
MAX UNITS
4.5 to
5.5
2
-
-
-
-
2
-
-
2
-
-
V
V
V
IH
Low Level Input Voltage,
4.5 to
5.5
0.8
0.8
0.8
V
IL
On Resistance, r
V
V
or V
V or
IL
0
-
4.5
-
-
-
-
-
-
-
-
-
-
70
-
160
-
-
-
-
-
-
-
-
-
200
-
-
-
-
-
-
-
-
-
240
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
ON
= 1mA, (Figure 15)
CC
CC
EE
I
V
O
IH
-
-
-
-4.5
0
4.5
4.5
-
40
90
-
120
150
180
to V
180
225
270
EE
-
-
-
-
-4.5
0
4.5
4.5
-
45
10
-
130
162
195
Maximum On Resistance
Between any Two
Channels, ∆r
ON
-
-
-
-
-
-
-
-
-
-
-4.5
4.5
5
Switch On/Off Leakage
Current, I
For Switch Off:
V
V
or
IL
When V = V
,
IZ
IS CC
IH
V
= V
;
OS
EE
1 and 2 Channels
4053
0
-5
0
6
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±0.1
±0.1
±0.1
±0.2
±0.2
±0.4
±0.1
-
-
-
-
-
-
-
±1
±1
±1
±2
±2
±4
±1
-
-
-
-
-
-
-
±1
±1
±1
±2
±2
±4
±1
µA
µA
µA
µA
µA
µA
µA
When V = V
,
EE
IS
= V
V
OS
CC
For Switch On:
All Applicable
Combinations of
V
4 Channels
4052
6
-5
0
5
and V
IS
OS
8 Channels
4051
Voltage Levels
6
-5
-
5
Control Input Leakage
-
(Note 4)
5.5
Current, I
IL
Quiescent Device
Current, I
When V = V
IS
,
V
or
0
5.5
5.5
-
-
-
-
-
8
-
-
-
80
-
-
-
160
320
490
µA
µA
µA
EE
CC
GND
V
= V
CC
OS
CC
I
= 0
O
When V = V
,
-4.5
16
160
450
IS
= V
CC
V
OS
EE
Additional Quiescent
Device Current
Per Input Pin: 1 Unit
Load
∆ICC
(Note 5)
V
-
4.5 to
5.5
100
360
CC
2.1
NOTES:
4. Any voltage between V
and GND.
CC
5. For dual supply systems theoretical worst case (V = 2.4V, V
= 5.5V) specification is 1.8mA.
I
CC
HCT Input Loading Table
UNIT LOADS
TYPE
4051, 4053
INPUT
All
(NOTE)
0.5
4052
All
0.4
NOTE: Unit load is ∆I
e.g., 360mA max. at 25 C.
limit specified in DC Specifications table,
CC
o
8
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
o
Switching Specifications V = 5V, T = 25 C, Input t , t = 6ns
CC
A
r r
TYPICAL
4052
4051
4053
C
L
PARAMETER
(pF)
HC
HCT
HC
HCT
HC
HCT
UNITS
Propagation Delay
Switch IN to OUT, t
, t
PHL PLH
15
15
15
-
4
4
4
4
4
4
ns
ns
ns
pF
Switch Turn-Off (S or E), t
Switch Turn-On (S or E), t
,
19
19
50
19
23
52
21
27
74
21
29
76
18
18
38
18
20
42
PHZ tPLZ
, t
PZH PZL
Power Dissipation Capacitance, C
(Note 6)
PD
NOTE:
6. C
P
is used to determine the dynamic power consumption, per package.
PD
= C
2
2
V
f + ∑ (C + C ) V f
CC O
D
PD CC
I
L
S
f
= output frequency
O
f = input frequency
I
C
C
= output load capacitance
= switch capacitance
L
S
V
= supply voltage
CC
Switching Specifications C = 50pF, Input t , t = 6ns
L
r r
AMBIENT TEMPERATURE, T
A
o
o
o
o
o
25 C
-40 C - 85 C
HC HCT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS
-55 C - 125 C
HC
HCT
HC
HCT
V
V
CC
EE
PARAMETER
(V)
(V)
Propagation Delay, Switch
0
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
60
12
10
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
90
18
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
18
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
In to Out, t
, t
PLH PHL
0
4.5
6
0
13
15
-4.5 4.5
8
10
10
-
12
12
-
Maximum Switch
Turn “Off” Delay
from S or E to
Switch Output
4051
4052
4053
0
0
0
2
4.5
6
225
45
38
32
250
50
43
38
210
42
36
29
-
280
56
340
68
45
-
56
-
68
-
48
57
t
, t
PHZ PLZ
-4.5 4.5
32
-
40
40
-
48
48
-
0
0
0
2
4.5
6
315
63
375
75
50
-
63
-
75
-
54
65
-4.5 4.5
38
-
48
48
-
57
57
-
0
0
0
2
4.5
6
265
53
315
63
44
-
55
-
66
-
45
54
-4.5 4.5
31
36
39
44
47
9
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)
L
r r
AMBIENT TEMPERATURE, T
A
o
o
o
o
o
25 C
-40 C - 85 C
HC HCT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS
-55 C - 125 C
HC
HCT
HC HCT
V
V
CC
EE
PARAMETER
Maximum Switch
Turn “On” Delay
from S or E to
Switch Output
(V)
(V)
4051
4052
4053
0
2
-
-
-
-
-
-
-
-
-
-
-
-
-
225
45
-
-
-
-
-
-
-
-
-
-
-
-
-
-
55
-
-
-
-
-
-
-
-
-
-
-
-
-
-
280
56
-
-
-
-
-
-
-
-
-
-
-
-
-
-
69
-
-
-
-
-
-
-
-
-
-
-
-
-
-
340
68
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
0
4.5
6
0
38
48
57
t
, t
PZL PZH
-4.5 4.5
32
39
-
40
49
-
48
59
-
0
0
0
2
4.5
6
325
65
405
81
490
98
70
-
68
-
105
-
55
69
83
-4.5 4.5
46
48
-
58
60
-
69
72
-
0
0
0
2
4.5
6
220
44
275
55
330
66
48
-
60
-
72
-
37
47
56
-4.5 4.5
31
34
10
39
43
10
47
51
10
Input (Control)
Capacitance, C
-
-
10
10
10
I
o
Analog Channel Specifications Typical Values at T = 25 C
A
HC/HCT
TYPES
V
(V)
V
(V)
HC/
HCT
EE
CC
PARAMETER
TEST CONDITIONS
UNITS
pF
Switch Input Capacitance, C
All
-
-
-
-
-
-
-
-
5
I
Common Output Capacitance, C
4051
4052
4053
4051
4052
4053
4051
4052
4053
25
pF
COM
12
pF
8
pF
Minimum Switch Frequency Response at -3dB, f
(Figures 12, 14, 16)
See Figure 3 (Notes 7, 8)
145
165
200
180
185
200
MHz
MHz
MHz
MHz
MHz
MHz
MAX
-2.25
-4.5
2.25
4.5
10
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
o
Analog Channel Specifications Typical Values at T = 25 C
A
HC/HCT
TYPES
V
(V)
V
(V)
HC/
HCT
EE
CC
PARAMETER
TEST CONDITIONS
UNITS
dB
Crosstalk Between any Two Switches (Note 10)
See Figure 4
(Notes 8, 9)
4051
4052
4053
4051
4052
4053
All
N/A
-2.25
2.25
(TBE)
(TBE)
N/A
dB
dB
dB
-4.5
4.5
(TBE)
(TBE)
0.035
0.018
dB
dB
Sinewave Distortion
See Figure 5
-2.25
-4.5
2.25
4.5
%
All
%
E or S to Switch Feedthrough Noise
See Figure 6
(Notes 8, 9)
4051
4052
4053
4051
4052
4053
4051
4052
4053
4051
4052
4053
mV
mV
mV
mV
mV
mV
dB
-2.25
-4.5
2.25
4.5
(TBE)
(TBE)
Switch “OFF” Signal Feedthrough (Figures 13, 15, 17)
See Figure 7
(Notes 8, 9)
-73
-65
-64
-75
-67
-66
-2.25
-4.5
2.25
4.5
dB
dB
dB
dB
dB
NOTES:
7. Adjust input voltage to obtain 0dBm at V
for f = 1MHz.
IN
OS
8. V is centered at (V
IS
- V )/2.
EE
CC
9. Adjust input for 0dBm.
10. Not applicable for HC/HCT4051.
11
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Test Circuits and Waveforms
V
CC
V
IS
R
SWITCH
ON
V
OS1
0.1µF
INPUT
R
C
f
= 1MHz SINEWAVE
IS
V
R = 50Ω
C = 10pF
CC
V
/2
CC
V
OS
SWITCH
ON
V
IS
V
CC
0.1µF
dB
METER
50Ω
10pF
R
SWITCH
OFF
V
OS2
V
/2
CC
dB
METER
V
/2
R
C
CC
V
/2
CC
FIGURE 3. FREQUENCY RESPONSE TEST CIRCUIT
FIGURE 4. CROSSTALK BETWEEN TWO SWITCHES TEST
CIRCUIT
E
V
CC
V
V
P-P
CC
V
OS
V = V
I
IH
V
IS
SWITCH
ALTERNATING
ON AND OFF
600Ω
SWITCH
ON
V
OS
SINE-
WAVE
V
OS
10µF
t , t ≤ 6ns
r
f
V
/2
V
CC
IS
600Ω
50pF
f
= 1MHz
10kΩ
50pF
CONT
50% DUTY
CYCLE
DISTORTION
METER
SCOPE
V
/2
CC
V
/2
CC
f
= 1kHz TO 10kHz
IS
FIGURE 5. SINEWAVE DISTORTION TEST CIRCUIT
FIGURE 6. CONTROL TO SWITCH FEEDTHROUGH NOISE
TEST CIRCUIT
f
≥ 1MHz SINEWAVE
IS
R = 50Ω
C = 10pF
V
CC
V
= V
R
C
IL
0.1µF
V
OS
SWITCH
OFF
V
IS
dB
METER
R
C
V
/2
V
/2
CC
CC
FIGURE 7. SWITCH OFF SIGNAL FEEDTHROUGH
12
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Test Circuits and Waveforms (Continued)
V
CC
t = 6ns
r
t = 6ns
f
90%
50%
SWITCH INPUT
10%
t
t
PLH
PHL
V
EE
90%
50%
10%
SWITCH OUTPUT
FIGURE 8A.
6ns
6ns
6ns
t
t
6ns
r
f
V
3V
CC
90%
2.7
E OR Sn
E OR Sn
1.3
50%
10%
0.3
GND
GND
t
t
t
t
PZL
PLZ
PZL
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
50%
50%
10%
90%
10%
90%
t
t
t
t
PZH
PHZ
PZH
PHZ
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
SWITCH ON
SWITCH OFF
SWITCH ON
SWITCH ON
SWITCH OFF
SWITCH ON
FIGURE 8B. HC TYPES
FIGURE 8C. HCT TYPES
FIGURE 8. SWITCH PROPAGATION DELAY, TURN-ON, TURN-OFF TIMES
V
FOR
V
FOR
AND t
PZL
EE
AND t
CC
R
= 1kΩ
L
t
t
PLZ
PZL
FOR
PLZ
OUT
TG
IN
TG
V
V
t
FOR
EE
IN
CC
AND t
C
50pF
OUT
L
50pF
t
AND t
PHZ
PZH
PHZ
PZH
FIGURE 9. SWITCH ON/OFF PROPAGATION DELAY TEST
CIRCUIT
FIGURE 10. SWITCH IN TO SWITCH OUT PROPAGATION
DELAY TEST CIRCUIT
13
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Typical Performance Curves
120
100
80
V
- V = 4.5V
EE
CC
60
V
- V = 6V
EE
CC
40
V
- V = 9V
EE
CC
20
1
2
3
4
5
6
7
8
9
INPUT SIGNAL VOLTAGE (V)
FIGURE 11. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE
0
0
-2
-4
-6
V
= 4.5V
CC
GND = -4.5V
= -4.5V
-20
-40
V
EE
V
= 2.25V
CC
GND = -2.25V
= -2.25V
R
= 50Ω
L
PIN 12 TO 3
V
EE
R
= 50Ω
L
V
= 2.25V
CC
GND = -2.25V
= -2.25V
PIN 12 TO 3
V
EE
-60
R
= 50Ω
L
PIN 12 TO 3
V
= 4.5V
CC
GND = -4.5V
= -4.5V
V
-80
EE
-8
R
= 50Ω
L
PIN 12 TO 3
-100
-10
10K
1M
FREQUENCY (Hz)
100K
1M
FREQUENCY (Hz)
10M
100M
10K
100K
10M 100M
FIGURE 12. CHANNEL ON BANDWIDTH (HC/HCT4051)
FIGURE 13. CHANNEL OFF FEEDTHROUGH (HC/HCT4051)
0
-2
-4
-6
0
V
= 2.25V
CC
GND = -2.25V
= -2.25V
V
= 4.5V
CC
GND = -4.5V
= -4.5V
-20
-40
-60
V
EE
V
EE
R
= 50Ω
PIN 4 TO 3
L
R
= 50Ω
L
PIN 4 TO 3
V
= 2.25V
CC
GND = -2.25V
= -2.25V
V
EE
R
= 50Ω
L
V
= 4.5V
PIN 4 TO 3
CC
GND = -4.5V
= -4.5V
V
EE
L
-80
-8
R
= 50Ω
PIN 4 TO 3
-100
10K
-10
10K
100K
1M
FREQUENCY (Hz)
10M
100M
100K
1M
FREQUENCY (Hz)
10M
100M
FIGURE 14. CHANNEL ON BANDWIDTH (HC/HCT4052)
FIGURE 15. CHANNEL OFF FEEDTHROUGH (HC/HCT4052)
14
’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053
Typical Performance Curves (Continued)
0
0
V
= 2.25V
CC
GND = -2.25V
= -2.25V
-20
-40
-60
V
V
= 4.5V
EE
CC
GND = -4.5V
= -4.5V
-1
-2
-3
-4
R
= 50Ω
L
PIN 5 TO 4
V
EE
R
= 50Ω
L
PIN 5 TO 4
V
= 4.5V
CC
GND = -4.5V
= -4.5V
V
= 2.25V
CC
V
EE
GND = -2.25V
R
= 50Ω
L
V
= -2.25V
= 50Ω
PIN 5 TO 4
EE
-80
R
L
PIN 5 TO 4
-100
10K
100K
1M
FREQUENCY (Hz)
10M
100M
10K
100K
1M
FREQUENCY (Hz)
10M
100M
FIGURE 16. CHANNEL ON BANDWIDTH (HC/HCT4053)
FIGURE 17. CHANNEL OFF FEEDTHROUGH (HC/HCT4053)
15
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
CDIP
CDIP
CDIP
CDIP
CDIP
CDIP
CDIP
PDIP
Drawing
5962-8775401EA
5962-8855601EA
5962-9065401MEA
CD54HC4051F
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
J
J
J
J
J
J
J
J
N
16
16
16
16
16
16
16
16
16
16
16
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
1
1
CD54HC4051F3A
CD54HC4052F
1
1
CD54HC4052F3A
CD54HC4053F
1
1
CD54HC4053F3A
CD54HCT4051F3A
CD74HC4051E
1
1
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC4051EE4
CD74HC4051M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
N
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4051M96
CD74HC4051M96E4
CD74HC4051M96G4
CD74HC4051ME4
CD74HC4051MG4
CD74HC4051MT
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4051MTE4
CD74HC4051MTG4
CD74HC4051NSR
CD74HC4051NSRE4
CD74HC4051NSRG4
CD74HC4051PWR
CD74HC4051PWRE4
CD74HC4051PWRG4
CD74HC4051PWT
CD74HC4051PWTE4
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
NS
NS
PW
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2008
Orderable Device
CD74HC4051PWTG4
CD74HC4052E
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
PDIP
N
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC4052EE4
CD74HC4052M
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SO
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4052M96
CD74HC4052M96E4
CD74HC4052M96G4
CD74HC4052ME4
CD74HC4052MG4
CD74HC4052MT
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4052MTE4
CD74HC4052MTG4
CD74HC4052NSR
CD74HC4052NSRE4
CD74HC4052NSRG4
CD74HC4052PW
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
PW
DB
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
SSOP
PDIP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4052PWE4
CD74HC4052PWG4
CD74HC4052PWR
CD74HC4052PWRE4
CD74HC4052PWRG4
CD74HC4052PWT
CD74HC4052PWTE4
CD74HC4052PWTG4
CD74HC4052SM
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4053E
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2008
Orderable Device
CD74HC4053EE4
CD74HC4053M
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
SOIC
D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4053M96
CD74HC4053M96E4
CD74HC4053M96G4
CD74HC4053ME4
CD74HC4053MG4
CD74HC4053MT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4053MTE4
CD74HC4053MTG4
CD74HC4053NSR
CD74HC4053NSRG4
CD74HC4053PW
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
PW
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PDIP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4053PWE4
CD74HC4053PWG4
CD74HC4053PWR
CD74HC4053PWRE4
CD74HC4053PWRG4
CD74HC4053PWT
CD74HC4053PWTE4
CD74HC4053PWTG4
CD74HCT4051E
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT4051EE4
CD74HCT4051M
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT4051M96
CD74HCT4051M96E4
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2008
Orderable Device
CD74HCT4051M96G4
CD74HCT4051ME4
CD74HCT4051MG4
CD74HCT4051MT
CD74HCT4051MTE4
CD74HCT4051MTG4
CD74HCT4052E
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
N
N
D
D
D
D
D
D
D
D
D
N
N
D
D
D
D
D
D
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT4052EE4
CD74HCT4052M
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT4052M96
CD74HCT4052M96E4
CD74HCT4052M96G4
CD74HCT4052ME4
CD74HCT4052MG4
CD74HCT4052MT
CD74HCT4052MTE4
CD74HCT4052MTG4
CD74HCT4053E
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT4053EE4
CD74HCT4053M
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HCT4053M96
CD74HCT4053M96E4
CD74HCT4053M96G4
CD74HCT4053ME4
CD74HCT4053MG4
CD74HCT4053MT
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
1-Apr-2008
Orderable Device
CD74HCT4053MTE4
CD74HCT4053MTG4
CD74HCT4053PWR
CD74HCT4053PWRE4
CD74HCT4053PWRG4
CD74HCT4053PWT
CD74HCT4053PWTE4
CD74HCT4053PWTG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CD74HC4051M96
CD74HC4051NSR
CD74HC4051PWR
CD74HC4052M96
CD74HC4052NSR
CD74HC4052PWR
CD74HC4053M96
CD74HC4053NSR
CD74HC4053PWR
CD74HCT4051M96
CD74HCT4052M96
CD74HCT4053M96
CD74HCT4053PWR
SOIC
SO
D
NS
PW
D
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
2000
2000
2500
2000
2000
2500
2000
2000
2500
2500
2500
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
12.4
16.4
16.4
12.4
16.4
16.4
12.4
16.4
16.4
16.4
12.4
6.5
8.2
7.0
6.5
8.2
7.0
6.5
8.2
7.0
6.5
6.5
6.5
7.0
10.3
10.5
5.6
2.1
2.5
1.6
2.1
2.5
1.6
2.1
2.5
1.6
2.1
2.1
2.1
1.6
8.0
12.0
8.0
16.0
16.0
12.0
16.0
16.0
12.0
16.0
16.0
12.0
16.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
TSSOP
SOIC
SO
10.3
10.5
5.6
8.0
NS
PW
D
12.0
8.0
TSSOP
SOIC
SO
10.3
10.5
5.6
8.0
NS
PW
D
12.0
8.0
TSSOP
SOIC
SOIC
SOIC
TSSOP
10.3
10.3
10.3
5.6
8.0
D
8.0
D
8.0
PW
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CD74HC4051M96
CD74HC4051NSR
CD74HC4051PWR
CD74HC4052M96
CD74HC4052NSR
CD74HC4052PWR
CD74HC4053M96
CD74HC4053NSR
CD74HC4053PWR
CD74HCT4051M96
CD74HCT4052M96
CD74HCT4053M96
CD74HCT4053PWR
SOIC
SO
D
NS
PW
D
16
16
16
16
16
16
16
16
16
16
16
16
16
2500
2000
2000
2500
2000
2000
2500
2000
2000
2500
2500
2500
2000
333.2
346.0
346.0
333.2
346.0
346.0
333.2
346.0
346.0
333.2
333.2
333.2
346.0
345.9
346.0
346.0
345.9
346.0
346.0
345.9
346.0
346.0
345.9
345.9
345.9
346.0
28.6
33.0
29.0
28.6
33.0
29.0
28.6
33.0
29.0
28.6
28.6
28.6
29.0
TSSOP
SOIC
SO
NS
PW
D
TSSOP
SOIC
SO
NS
PW
D
TSSOP
SOIC
SOIC
SOIC
TSSOP
D
D
PW
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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