CD74HC42M96 [TI]
HC/UH SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, PDSO16, SOIC-16;型号: | CD74HC42M96 |
厂家: | TEXAS INSTRUMENTS |
描述: | HC/UH SERIES, DECIMAL DECODER/DRIVER, INVERTED OUTPUT, PDSO16, SOIC-16 驱动 光电二极管 输出元件 |
文件: | 总6页 (文件大小:30K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CD54/74HC42,
CD74HCT42
Data sheet acquired from Harris Semiconductor
SCHS133A
High Speed CMOS Logic
August 1997 - Revised May 2000
BCD To Decimal Decoder (1 of 10)
Features
Description
• Buffered Inputs and Outputs
The ’HC42 and CD74HCT42 BCD-to-Decimal Decoders
utilize silicon-gate CMOS technology to achieve operating
speeds similar to LSTTL decoders with the low power
consumption of standard CMOS integrated circuits. These
devices have the capability of driving 10 LSTLL loads and
are compatible with the standard LS logic family. One of ten
outputs (low on select) is selected in accordance with the
BCD input. Non-valid BCD inputs result in none of the
• Typical Propagation Delay: 12ns at V
o
= 5V,
[ /Title
(CD74H
C42,
CC
C = 15pF, T = 25 C
L
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
CD74H
CT42)
/Subject
(High
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C outputs being selected (all outputs are high).
• Balanced Propagation Delay and Transition Times
Ordering Information
Speed
• Significant Power Reduction Compared to LSTTL
o
CMOS
Logic
BCD To
Deci-
PART NUMBER
CD54HC42F3A
CD74HC42E
CD74HC42M
CD74HCT42E
NOTES:
TEMP. RANGE ( C)
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
Logic ICs
• HC Types
- 2V to 6V Operation
-55 to 125
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
-55 to 125
at V
= 5V
CC
• HCT Types
-55 to 125
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
2. Die for this part number is available which meets all electrical
specifications. Please contact your local TI sales office or cus-
tomer service for ordering information.
Pinout
CD54HC42
(CERDIP)
CD74HC42, CD74HCT42
(PDIP, SOIC)
TOP VIEW
Y0
Y1
1
2
3
4
5
6
7
8
16 V
CC
15 A0
14 A1
13 A2
12 A3
11 Y9
10 Y8
Y2
Y3
Y4
Y5
Y6
9
Y7
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2000 Texas Instruments Incorporated.
1
CD54/74HC42, CD74HCT42
Functional Diagram
1
Y0
15
14
13
12
2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
A0
A1
A2
A3
3
4
5
6
7
9
10
11
TRUTH TABLE
INPUTS
OUTPUTS
A3
L
A2
L
A1
L
A0
L
Y0
L
Y1
Y2
H
H
L
Y3
H
H
H
L
Y4
Y5
Y6
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
L
Y8
H
H
H
H
H
H
H
H
L
Y9
H
H
H
H
H
H
H
H
H
L
H
L
H
H
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
L
H
H
H
H
L
H
L
H
H
H
NOTE: H = High Voltage Level, L = Low Voltage Level
2
CD54/74HC42, CD74HCT42
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
For V < -0.5V or V > V
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
190
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
(SOIC - Lead Tips Only)
DC V
or Ground Current, I
I
. . . . . . . . . . . . . . . . . .±50mA
CC
CC or GND
Operating Conditions
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
3
CD54/74HC42, CD74HCT42
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HCT TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
V
4.5 to
5.5
100
360
450
CC
-2.1
NOTE: For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
INPUT
All
UNIT LOADS
1
NOTE: Unit Load is ∆I
360µA max at 25 C.
limit specified in DC Electrical Table, e.g.
CC
o
Switching Specifications Input t , t = 6ns
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
SYMBOL CONDITIONS
PARAMETER
HC TYPES
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay,
Input to Y (Figure 1)
t
t
C = 50pF
2
-
-
-
150
30
26
-
-
-
-
-
-
-
-
-
190
38
33
-
-
-
-
-
-
-
-
-
225
45
38
-
ns
ns
ns
ns
ns
ns
ns
pF
PLH, PHL
L
4.5
6
-
-
-
-
-
-
-
-
Any Input to Y
t
, t
C = 15pF
5
12
-
PLH PHL
L
Output Transition Time
(Figure 1)
t
, t
TLH THL
C = 50pF
L
2
75
15
13
10
95
19
16
10
110
22
19
10
4.5
6
-
-
Input Capacitance
C
-
-
-
IN
4
CD54/74HC42, CD74HCT42
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Power Dissipation Capacitance
(Notes 4, 5)
C
-
5
-
65
-
-
-
-
-
-
pF
PD
HCT TYPES
Propagation Delay,
Input to Y (Figure 2)
t
, t
PLH PHL
C = 50pF
4.5
-
35
-
44
-
53
ns
L
Any Input to Y
t
, t
PLH PHL
C = 15pF
5
-
-
14
-
-
-
-
-
-
-
-
ns
ns
L
Output Transition Time
(Figure 2)
t
, t
TLH THL
C = 50pF
L
4.5
15
19
22
Input Capacitance
C
-
-
-
-
-
-
10
-
-
-
10
-
-
-
10
-
pF
pF
IN
Power Dissipation Capacitance
(Notes 4, 5)
C
5
70
PD
NOTES:
4. C
is used to determine the dynamic power consumption, per package.
2
PD
5. P = V
f (C
PD
+ C ) where: f = Input Frequency, C = Output Load Capacitance, V = Supply Voltage.
CC
D
CC
i
L
i
L
Test Circuits and Waveforms
t = 6ns
t = 6ns
f
r
t = 6ns
f
t = 6ns
r
V
CC
3V
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
TLH
THL
t
t
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
t
t
PLH
PLH
PHL
PHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 2000, Texas Instruments Incorporated
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