CD74HC4511MTE4 [TI]
BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS; BCD到7段锁存器/解码器/驱动器
| 型号： | CD74HC4511MTE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS |
| 文件： | 总17页 (文件大小：428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢈꢃ ꢂꢅꢅ
ꢉꢀꢁ ꢊꢈꢋ ꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑ ꢒꢈ ꢀꢄꢓ ꢁꢍꢀꢋ ꢁꢍ ꢔꢓ ꢁꢔ ꢕ ꢖꢍ ꢔ ꢌ
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
CD54HC4511 . . . F PACKAGE
D
D
2-V to 6-V V
Operation (’HC4511)
CC
CD74HC4511 . . . E, M, OR PW PACKAGE
CD74HCT4511 . . . E PACKAGE
(TOP VIEW)
4.5-V to 5.5-V V
(CD74HCT4511)
Operation
CC
D
High-Output Sourcing Capability
− 7.5 mA at 4.5 V (CD74HCT4511)
− 10 mA at 6 V (’HC4511)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
f
D
D
BCD
Inputs
CC
1
2
g
a
b
c
d
e
LT
BL
LE
D
D
D
D
D
Input Latches for BCD Code Storage
Lamp Test and Blanking Capability
7-Segment
Outputs
Balanced Propagation Delays and
Transition Times
D
BCD
Inputs
3
D
0
Significant Power Reduction Compared to
LSTTL Logic ICs
GND
’HC4511
− High Noise Immunity,
DISPLAY
N
or N = 30% of V
at V
= 5 V
IL
IH
CC
CC
D
CD74HCT4511
− Direct LSTTL Input Logic Compatibility,
= 0.8 V Maximum, V = 2 V Minimum
0
1
2
3
4
5
6
7
8
9
a
V
IL
IH
f
g
b
− CMOS Input Compatibility, I ≤ 1 µA
I
at V , V
e
c
OL OH
d
description/ordering information
The CD54HC4511, CD74HC4511, and CD74HCT4511 are BCD-to-7 segment latch/decoder/drivers with four
address inputs (D −D ), an active-low blanking (BL) input, lamp-test (LT) input, and a latch-enable (LE) input
0
3
that, when high, enables the latches to store the BCD inputs. When LE is low, the latches are disabled, making
the outputs transparent to the BCD inputs.
These devices have standard-size output transistors, but are capable of sourcing (at standard V
to 7.5 mA at 4.5 V. The HC types can supply up to 10 mA at 6 V.
levels) up
OH
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
CD74HC4511E
CD74HC4511E
CD74HCT4511E
PDIP − E
SOIC − M
Tube of 25
CD74HCT4511E
CD74HC4511M
Tube of 40
Reel of 2500
Reel of 250
Reel of 2000
Reel of 250
Tube of 25
CD74HC4511M96
CD74HC4511MT
CD74HC4511PWR
CD74HC4511PWT
CD54HC4511F3A
HC4511M
−55°C to 125°C
TSSOP − PW
CDIP − F
HJ4511
CD54HC4511F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢀ ꢃ ꢂꢅꢅ ꢆ ꢀꢁ ꢇ ꢃꢄ ꢀꢃ ꢂ ꢅꢅ ꢆ ꢀꢁ ꢇ ꢃꢄ ꢀꢈ ꢃꢂ ꢅꢅ
ꢉ ꢀꢁꢊꢈꢋꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑꢒꢈꢀ ꢄꢓ ꢁ ꢍꢀ ꢋꢁ ꢍꢔꢓ ꢁꢔꢕ ꢖꢍ ꢔꢌ
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
FUNCTION TABLE
INPUTS
OUTPUTS
LE BL LT
D
D
D
D
0
a
H
L
b
H
L
c
H
L
d
H
L
e
H
L
H
L
H
L
L
L
H
L
H
L
L
L
L
L
L
f
g
H
L
DISPLAY
3
2
1
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
L
X
X
X
X
H
L
8
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
L
X
L
X
L
X
L
Blank
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
L
H
L
H
L
L
0
L
L
L
H
L
L
1
L
L
H
H
L
H
H
L
H
H
L
L
H
H
H
H
H
L
2
L
L
H
L
H
H
H
H
H
H
H
L
L
3
4
L
H
H
H
H
L
H
H
H
L
L
L
H
L
H
L
H
H
L
5
L
H
H
L
L
6
L
H
L
H
H
H
L
H
H
H
L
7
H
H
H
H
H
H
H
H
X
H
L
H
H
L
H
H
L
8
L
L
H
L
9
L
H
H
L
L
Blank
Blank
Blank
Blank
Blank
L
H
L
L
L
L
L
L
L
H
H
H
H
X
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
X
L
L
L
L
L
L
H
X
L
†
L
†
L
†
L
†
L
†
L
†
L
†
Blank
†
X = Don’t care
†
Depends on BCD code previously applied when LE = L
NOTE: Display is blank for all illegal input codes (BCD > HLLH).
function diagram
3
LT
13
12
11
10
9
a
7
1
D
0
b
c
d
e
D
D
D
1
2
3
7-Segment
Outputs
BCD
Inputs
2
6
15
14
f
g
5
4
LE
BL
V
= 8
SS
DD
V
= 16
2
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ꢀꢁꢂ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢈꢃ ꢂꢅꢅ
ꢉꢀꢁ ꢊꢈꢋ ꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑ ꢒꢈ ꢀꢄꢓ ꢁꢍꢀꢋ ꢁꢍ ꢔꢓ ꢁꢔ ꢕ ꢖꢍ ꢔ ꢌ
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
logic diagram
4
BL
13
a
6
D
3
D
Q
12
b
Latch
LE
LE
LE
Q
LE
11
c
2
D
2
D
Q
Latch
LE
10
d
LE
LE
Q
LE
1
D
1
D
Q
Latch
LE
LE
LE
Q
LE
9
e
7
D
0
D
Q
Latch
LE
15
f
LE
LE
Q
LE
14
g
5
LE
LE
LE
3
LT
3
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ꢉ ꢀꢁꢊꢈꢋꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑꢒꢈꢀ ꢄꢓ ꢁ ꢍꢀ ꢋꢁ ꢍꢔꢓ ꢁꢔꢕ ꢖꢍ ꢔꢌ
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input diode current, I (V < −0.5 V or V > V + 0.5 V) ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
O
Output diode current, I
(V < −0.5 V or V > V
+ 0.5V) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O
CC
Continuous output source or sink current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
Package thermal impedance, θ (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
JA
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Lead temperature (during soldering):
At distance 1/16 1/32 in (1.59 0.79 mm) from case for 10 s maximum . . . . . . . . . . . . . . . . . . . . . 265°C
Unit inserted into a PC board (minimum thickness 1/16 in, 1.59 mm),
with solder contacting lead tips only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions for ’HC4511 (see Note 3)
T
= −55°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
UNIT
MIN
2
MAX
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
6
6
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
= 4.5 V
= 6 V
High-level input voltage
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
= 4.5 V
= 6 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
0
0
V
0
0
V
V
V
V
I
CC
CC
CC
Output voltage
V
CC
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
1000
500
1000
500
t
t
Input transition (rise and fall) time
= 4.5 V
= 6 V
ns
400
400
400
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢈꢃ ꢂꢅꢅ
ꢉꢀꢁ ꢊꢈꢋ ꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑ ꢒꢈ ꢀꢄꢓ ꢁꢍꢀꢋ ꢁꢍ ꢔꢓ ꢁꢔ ꢕ ꢖꢍ ꢔ ꢌ
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
recommended operating conditions for CD74HCT4511 (see Note 4)
T
= −55°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
0.8
V
V
V
V
V
V
V
V
CC
CC
CC
Output voltage
V
O
CC
CC
CC
t
t
Input transition (rise and fall) time
500
500
500
ns
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
’HC4511
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= −55°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
1.9
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
4.4
4.4
I
= −20 µA
OH
5.9
5.9
V
V
V = V or V
IH
V
OH
I
IL
I
I
= −7.5 mA
= −10 mA
4.5 V
6 V
3.98
5.48
3.84
5.34
OH
OH
2 V
0.1
0.1
0.1
0.26
0.26
0.1
8
0.1
0.1
0.1
0.4
0.4
1
0.1
0.1
0.1
0.33
0.33
1
4.5 V
6 V
I
= 20 µA
OL
V = V or V
V
OL
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
OL
= 5.2 mA
OL
I
I
V = V
or 0
6 V
µA
µA
pF
I
I
CC
V = V
or 0,
I
O
= 0
6 V
160
10
80
CC
I
CC
C
10
10
i
5
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ꢀ ꢁꢂꢃ ꢄꢀ ꢃ ꢂꢅꢅ ꢆ ꢀꢁ ꢇ ꢃꢄ ꢀꢃ ꢂ ꢅꢅ ꢆ ꢀꢁ ꢇ ꢃꢄ ꢀꢈ ꢃꢂ ꢅꢅ
ꢉ ꢀꢁꢊꢈꢋꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑꢒꢈꢀ ꢄꢓ ꢁ ꢍꢀ ꢋꢁ ꢍꢔꢓ ꢁꢔꢕ ꢖꢍ ꢔꢌ
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
CD74HCT4511
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= −55°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= −20 µA
= −4 mA
= 20 µA
= 4 mA
OH
OH
OL
OL
V
V
V = V or V
IH
4.5 V
4.5 V
V
V
OH
I
IL
3.98
3.7
3.84
0.1
0.26
0.1
8
0.1
0.4
1
0.1
0.33
1
V = V or V
OL
I
IH
IL
I
I
V = V
to GND
or 0,
5.5 V
5.5 V
µA
µA
I
I
CC
V = V
I
O
= 0
160
80
CC
I
CC
One input at V
Other inputs at 0 or V
CC
− 2.1 V,
CC
†
4.5 V to 5.5 V
100
360
10
490
10
450
10
µA
∆I
CC
C
pF
i
†
Additional quiescent supply current per input pin, TTL inputs high, 1 unit load. For dual-supply systems, theoretical worst-case
(V = 2.4 V, V = 5.5 V) specification is 1.8 mA.
I
CC
HCT INPUT LOADING TABLE
‡
INPUT
LT, LE
BL, Dn
UNIT LOADS
1.5
0.3
‡
Unit load is ∆I
CC
limit specified in electrical
characteristics table, e.g., 360 µA maximum at
25°C.
’HC4511 timing requirements over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
T
= −55°C
T = −40°C
A
TO 85°C
A
T
A
= 25°C
TO 125°C
V
CC
UNIT
MIN
80
16
14
60
12
10
3
MAX
MIN
120
24
20
90
18
15
3
MAX
MIN
100
20
17
75
15
13
3
MAX
2 V
4.5 V
6 V
t
w
t
su
t
h
Pulse duration, LE low
ns
2 V
4.5 V
6 V
Setup time, BCD inputs before LE↑
Hold time, BCD inputs before LE↑
ns
2 V
4.5 V
6 V
3
3
3
ns
3
3
3
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢈꢃ ꢂꢅꢅ
ꢉꢀꢁ ꢊꢈꢋ ꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑ ꢒꢈ ꢀꢄꢓ ꢁꢍꢀꢋ ꢁꢍ ꢔꢓ ꢁꢔ ꢕ ꢖꢍ ꢔ ꢌ
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
’HC4511
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
T
= −55°C
T = −40°C
A
A
T
A
= 25°C
FROM
(INPUT)
TO
LOAD
TO 125°C
TO 85°C
PARAMETER
V
UNIT
CC
(OUTPUT) CAPACITANCE
MIN
TYP
MAX
300
60
MIN MAX
MIN
MAX
375
75
2 V
4.5 V
6 V
450
90
C
C
= 50 pF
= 15 pF
L
L
D
Output
Output
Output
n
51
77
64
5 V
25
23
18
13
2 V
270
54
405
81
340
68
4.5 V
6 V
C
C
= 50 pF
= 15 pF
L
LE
BL
LT
46
69
58
5 V
L
t
pd
ns
2 V
220
44
330
66
275
55
4.5 V
6 V
C
C
= 50 pF
= 15 pF
L
L
37
56
47
5 V
2 V
160
32
240
48
200
40
4.5 V
6 V
C
C
C
= 50 pF
= 15 pF
= 50 pF
L
L
L
Output
Any
27
41
34
5 V
2 V
75
15
13
110
22
95
19
16
t
t
4.5 V
6 V
ns
19
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢀ ꢃ ꢂꢅꢅ ꢆ ꢀꢁ ꢇ ꢃꢄ ꢀꢃ ꢂ ꢅꢅ ꢆ ꢀꢁ ꢇ ꢃꢄ ꢀꢈ ꢃꢂ ꢅꢅ
ꢉ ꢀꢁꢊꢈꢋꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑꢒꢈꢀ ꢄꢓ ꢁ ꢍꢀ ꢋꢁ ꢍꢔꢓ ꢁꢔꢕ ꢖꢍ ꢔꢌ
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
CD74HCT4511
timing requirements over recommended operating free-air temperature range V
otherwise noted) (see Figure 2)
= 4.5 V (unless
CC
T
= −55°C
T
= −40°C
TO 85°C
A
A
T
A
= 25°C
TO 125°C
UNIT
MIN
16
16
5
MAX
MIN
24
24
5
MAX
MIN
20
20
5
MAX
t
w
t
su
t
h
Pulse duration, LE low
ns
ns
ns
Setup time, BCD inputs before LE↑
Hold time, BCD inputs before LE↑
CD74HCT4511
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
T
= −55°C
T = −40°C
A
A
T
A
= 25°C
FROM
(INPUT)
TO
LOAD
TO 125°C
TO 85°C
PARAMETER
V
CC
UNIT
(OUTPUT) CAPACITANCE
MIN
TYP
MAX
MIN MAX
MIN
MAX
C
C
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
= 15 pF
= 50 pF
4.5 V
5 V
60
90
81
66
50
22
75
L
L
D
Output
Output
Output
n
25
23
18
13
C
C
4.5 V
5 V
54
44
33
15
68
55
41
19
L
LE
BL
LT
L
t
t
ns
ns
pd
C
C
C
C
C
4.5 V
5 V
L
L
L
L
L
4.5 V
5 V
Output
Any
4.5 V
t
operating characteristics, V
= 5 V, T = 25°C
CC
A
PARAMETER
TYP
114
110
UNIT
’HC4511
†
C
Power dissipation capacitance
pF
pd
CD74HCT4511
†
C
is used to determine the dynamic power consumption, per package.
pd
2
2
f
P
D
= C
V
f + ∑ C
i
V
CC
pd CC
L
o
where: f = input frequency
i
o
C
f
= output frequency
= output load capacitance
= supply voltage
L
V
CC
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢃꢂ ꢅꢅ ꢆ ꢀꢁꢇ ꢃ ꢄꢀ ꢈꢃ ꢂꢅꢅ
ꢉꢀꢁ ꢊꢈꢋ ꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑ ꢒꢈ ꢀꢄꢓ ꢁꢍꢀꢋ ꢁꢍ ꢔꢓ ꢁꢔ ꢕ ꢖꢍ ꢔ ꢌ
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION − ’HC4511
V
CC
PARAMETER
S1
S2
t
Open
Closed
Open
Closed
Open
PZH
S1
S2
t
en
Test
t
t
t
PZL
PHZ
PLZ
Point
R
= 1 kΩ
L
From Output
Under Test
Closed
t
t
dis
pd
C
Closed
Open
Open
Open
L
(see Note A)
or t
t
t
w
LOAD CIRCUIT
V
CC
Input
50% V
50% V
CC
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
V
CC
Reference
Input
V
CC
50% V
CC
CLR
Input
50% V
CC
0 V
0 V
t
t
h
su
t
rec
V
CC
CC
0 V
Data
Input
90%
90%
V
CC
50%
10%
50% V
10%
50% V
CC
CC
CLK
t
t
f
0 V
r
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
V
CC
V
CC
Input
50% V
CC
50% V
Output
Control
50% V
50% V
CC
CC
0 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
In-Phase
Output
90%
≈V
Output
Waveform 1
(see Note B)
CC
50%
10%
50% V
10%
CC
50% V
CC
V
OL
10%
V
OL
t
t
f
r
t
t
PHL
90%
PLH
t
t
PZH
PHZ
V
V
OH
90%
Out-of-Phase
Output
50% V
10%
50%
10%
Output
Waveform 2
(see Note B)
V
OH
CC
90%
50% V
CC
OL
t
f
t
≈0 V
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. includes probe and test-fixture capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
max
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄꢀ ꢃ ꢂꢅꢅ ꢆ ꢀꢁ ꢇ ꢃꢄ ꢀꢃ ꢂ ꢅꢅ ꢆ ꢀꢁ ꢇ ꢃꢄ ꢀꢈ ꢃꢂ ꢅꢅ
ꢉ ꢀꢁꢊꢈꢋꢊꢇ ꢌꢍ ꢎꢏ ꢍꢐ ꢈ ꢑꢒꢈꢀ ꢄꢓ ꢁ ꢍꢀ ꢋꢁ ꢍꢔꢓ ꢁꢔꢕ ꢖꢍ ꢔꢌ
SCHS279D − DECEMBER 1998 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION − CD74HCT4511
V
CC
PARAMETER
S1
S2
t
Open
Closed
Open
Closed
Open
PZH
S1
S2
Test
Point
t
en
t
t
t
R
= 1 kΩ
PZL
PHZ
PLZ
L
From Output
Under Test
Closed
t
t
dis
pd
C
L
Closed
Open
Open
Open
(see Note A)
or t
t
t
w
LOAD CIRCUIT
V
CC
Input
50% V
50% V
CC
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
V
CC
Reference
Input
V
CC
50% V
CC
CLR
Input
50% V
CC
0 V
0 V
t
t
h
su
t
rec
V
CC
CC
0 V
Data
Input
90%
90%
V
CC
50%
10%
50% V
10%
50% V
CC
CC
CLK
t
t
f
0 V
r
VOLTAGE WAVEFORMS
RECOVERY TIME
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
V
CC
V
CC
Input
50% V
CC
50% V
Output
Control
50% V
50% V
CC
CC
0 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
OH
In-Phase
Output
90%
≈V
Output
Waveform 1
(see Note B)
CC
50%
10%
50% V
10%
CC
V
50% V
CC
10%
OL
V
OL
t
t
f
r
t
t
PHL
90%
PLH
t
t
PZH
PHZ
V
V
OH
90%
Out-of-Phase
Output
50% V
10%
50%
10%
Output
Waveform 2
(see Note B)
V
OH
CC
90%
50% V
CC
OL
t
f
t
≈0 V
r
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. includes probe and test-fixture capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
max
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
PDIP
Drawing
5962-8773301EA
CD54HC4511F3A
CD74HC4511E
ACTIVE
ACTIVE
ACTIVE
J
J
16
16
16
1
1
TBD
TBD
A42 SNPB
A42 SNPB
N / A for Pkg Type
N / A for Pkg Type
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HC4511EE4
CD74HC4511M
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SOIC
N
D
16
16
16
16
16
16
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4511M96
CD74HC4511M96E4
CD74HC4511ME4
CD74HC4511MT
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
CD74HC4511MTE4
CD74HC4511PWR
CD74HC4511PWRE4
CD74HC4511PWT
CD74HC4511PWTE4
CD74HCT4511E
SOIC
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
PDIP
PW
PW
PW
PW
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CD74HCT4511EE4
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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Copyright 2006, Texas Instruments Incorporated
相关型号：
CD74HC4511MTG4
HC/UH SERIES, SEVEN SEGMENT DECODER/DRIVER, TRUE OUTPUT, PDSO16, GREEN, PLASTIC, MS-012AC, SOIC-16
TI
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