CD74HC540M96 [TI]
High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State; 高速CMOS逻辑八路缓冲器和线路驱动器，三态
| 型号： | CD74HC540M96 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State |
| 文件： | 总16页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD54/74HC540, CD74HCT540,
CD54/74HC541, CD54/74HCT541
Data sheet acquired from Harris Semiconductor
SCHS189C
High-Speed CMOS Logic
Octal Buffer and Line Drivers, Three-State
January 1998 - Revised July 2004
Features
Description
• ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting The ’HC540 and CD74HCT540 are Inverting Octal Buffers
and Line Drivers with Three-State Outputs and the capability
to drive 15 LSTTL loads. The ’HC541 and ’HCT541 are Non-
• ’HC541, ’HCT541 . . . . . . . . . . . . . . . . . . . . . . Non-Inverting
[ /Title
(CD74
HC540
,
CD74
HCT54
0,
CD74
HC541
,
CD74
HCT54
Inverting Octal Buffers and Line Drivers with Three-State Out-
puts that can drive 15 LSTTL loads. The Output Enables
(OE1) and (OE2) control the Three-State Outputs. If either
OE1 or OE2 is HIGH the outputs will be in the high imped-
ance state. For data output OE1 and OE2 both must be LOW.
• Buffered Inputs
• Three-State Outputs
• Bus Line Driving Capability
• Typical Propagation Delay = 9ns at V
o
= 5V,
CC
Ordering Information
C = 15pF, T = 25 C
L
A
TEMP. RANGE
o
• Fanout (Over Temperature Range)
PART NUMBER
CD54HC540F3A
CD54HC541F3A
CD54HCT541F3A
CD74HC540E
( C)
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
CD74HC540M
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
CD74HC540M96
CD74HC541E
• HC Types
- 2V to 6V Operation
CD74HC541M
20 Ld SOIC
20 Ld SOIC
20 Ld TSSOP
20 Ld TSSOP
20 Ld PDIP
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
CD74HC541M96
CD74HC541PW
CD74HC541PWR
CD74HCT540E
CD74HCT540M
CD74HCT540M96
CD74HCT541E
CD74HCT541M
CD74HCT541M96
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
20 Ld SOIC
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
Pinouts
CD54HC540
(CERDIP)
CD54HC541, CD54HCT541
(CERDIP)
CD74HC540, CD74HCT540
(PDIP, SOIC)
CD74HC541
(PDIP, SOIC, TSSOP)
CD74HCT541
TOP VIEW
(PDIP, SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
9
V
OE
A0
A1
A2
A3
A4
A5
A6
A7
20
19
CC
OE2
1
2
3
4
5
6
7
8
9
V
OE1
A0
A1
A2
A3
A4
A5
A6
A7
20
19
CC
18 Y0
17 Y1
16 Y2
OE2
18 Y0
17 Y1
16 Y2
15
Y3
14 Y4
13 Y5
15
Y3
14 Y4
13 Y5
12
Y6
GND 10
11 Y7
12
Y6
GND 10
11 Y7
Functional Diagram
OE
OE
B
A
540 541
D
D
Y
Y
0
0
0
Y
Y
Y
1
1
1
D
Y
2
4
6
2
2
D
Y
Y
3
3
3
D
D
Y
Y
4
4
Y
Y
5
5
5
D
Y
Y
6
6
D
Y
Y
7
7
7
2
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
TRUTH TABLE
INPUTS
OUTPUTS
OE1
L
OE2
L
An
H
X
540
L
541
H
H
X
Z
Z
X
H
X
Z
Z
L
L
L
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X= Don’t Care
Z = High Impedance
3
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
CC
DC Input Diode Current, I
For V < -0.5V or V > V
IK
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
DC Output Diode Current, I
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
o
DC Drain Current, per Output, I
O
o
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
O
CC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C
DC Output Source or Sink Current per Output Pin, I
O
(SOIC - Lead Tips Only)
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-6
4.5
6
3.98
-
3.84
-
3.7
-
-7.8
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
6
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
7.8
-
Input Leakage
Current
I
V
or
6
I
CC
GND
4
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
O
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
Three- State Leakage
Current
I
V
or V
V
=
or
6
-
-
±0.5
-
±5.0
-
±10
µA
OZ
IL
IH
O
V
CC
GND
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-6
0.02
6
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
5.5
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
-
160
±10
CC
CC
GND
Three- State Leakage
Current
I
V
or V
V =
O
±0.5
±5.0
OZ
IL
IH
V
or
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
CC
(Note 2)
V
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
CC
-2.1
NOTE:
2. For dual-supply systems theoretical worst case (V = 2.4V, V
I
= 5.5V) specification is 1.8mA.
CC
HCT Input Loading Table
UNIT LOADS
INPUT
A0 - A7
OE2
HCT540
1
HCT541
0.4
0.75
1.15
0.75
OE1
1.15
NOTE: Unit Load is ∆I limit specific in DC Electrical Specifications
CC
o
Table, e.g., 360µA max. at 25 C.
5
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
Switching Specifications C = 50pF, Input t , t = 6ns
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
HC TYPES
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
MIN
MAX UNITS
CC
Propagation Delay
t
, t
PLH PHL
C
= 50pF
L
Data to Outputs (540)
2
-
-
-
110
22
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
140
28
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
165
33
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
9
-
L
L
L
6
-
19
115
23
-
24
145
29
-
28
175
35
-
Data to Outputs (541)
t
t
t
t
, t
2
-
-
PLZ PHZ
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
-
9
-
L
L
L
6
-
20
160
32
-
25
200
40
-
30
240
48
-
Output Enable and Disable
to Outputs (540)
, t
PLZ PHZ
2
-
-
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
-
13
-
L
L
L
6
-
27
160
32
-
34
200
40
-
41
240
48
-
Output Enable and Disable
to Outputs (541)
, t
PLZ PHZ
2
-
-
4.5
5
-
-
C
C
C
= 15pF
= 50pF
= 50pF
-
14
-
L
L
L
6
-
23
60
12
10
10
20
29
75
15
13
10
20
35
90
18
15
10
20
Output Transition Time
Input Capacitance
, t
THL TLH
2
-
-
4.5
6
-
-
-
-
C
C
= 50pF
-
-
10
20
-
I
L
Three-State Output
Capacitance
C
-
-
O
Power Dissipation Capacitance
(Notes 3, 4) (540)
C
C
C
C
= 15pF
= 15pF
5
5
-
-
50
48
-
-
-
-
-
-
-
-
-
-
pF
pF
PD
PD
L
Power Dissipation Capacitance
(Notes 3, 4) (541)
L
HCT TYPES
Propagation Delay
t
t
PHL, PLH
Data to Outputs (540)
C
C
C
C
C
C
C
C
= 50pF
= 15pF
= 50pF
= 15pF
= 50pF
= 15pF
= 50pF
= 50pF
4.5
5
-
-
-
9
-
24
-
-
-
-
-
-
-
-
-
30
-
-
-
-
-
-
-
-
-
36
-
ns
ns
ns
ns
ns
ns
ns
pF
L
L
L
L
L
L
L
L
Data to Outputs (541)
t
t
t
t
4.5
5
-
28
-
35
-
42
-
PHL, PLH
-
11
-
Output Enable and Disable
to Outputs (540, 541)
, t
PLZ PHZ
4.5
5
-
35
-
44
-
53
-
-
14
-
Output Transition Time
Input Capacitance
, t
TLH THL
4.5
-
-
12
10
15
10
18
10
C
10
-
I
6
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541
Switching Specifications C = 50pF, Input t , t = 6ns (Continued)
L
r f
o
o
-40 C TO
-55 C TO
o
o
o
25 C
85 C
125 C
TEST
PARAMETER
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
20
MIN
MAX UNITS
CC
Three-State Output
Capacitance
C
-
-
20
-
20
-
-
20
pF
O
Power Dissipation Capacitance
(Notes 3, 4) (540, 541)
C
C
= 15pF
5
-
55
-
-
-
-
-
pF
PD
L
NOTES:
3. C
is used to determine the dynamic power consumption, per channel.
2
PD
4. P = V
f (C
PD
+ C ) where f = Input Frequency, C = Output Load Capacitance, V
= Supply Voltage.
D
CC
i
L
i
L
CC
Test Circuits and Waveforms
t = 6ns
f
t = 6ns
t = 6ns
t = 6ns
r
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
6ns
t
6ns
t
6ns
r
f
V
3V
CC
OUTPUT
DISABLE
OUTPUT
DISABLE
90%
2.7
50%
t
1.3
10%
0.3
GND
GND
t
t
t
t
PZL
PZL
PLZ
PLZ
OUTPUT LOW
TO OFF
OUTPUT LOW
TO OFF
50%
50%
1.3V
10%
90%
10%
90%
t
t
PZH
PHZ
PHZ
t
PZH
OUTPUT HIGH
TO OFF
OUTPUT HIGH
TO OFF
1.3V
OUTPUTS
ENABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
7
Test Circuits and Waveforms (Continued)
OTHER
OUTPUT
= 1kΩ
INPUTS
TIED HIGH
OR LOW
IC WITH
THREE-
STATE
R
L
V
FOR t AND t
PLZ
CC
GND FOR t
PZL
AND t
PHZ
PZH
C
L
OUTPUT
50pF
OUTPUT
DISABLE
NOTE: Open drain waveforms t
and t are the same as those for three-state shown on the left. The test circuit is Output R = 1kΩ to
PZL L
PLZ
V
, C = 50pF.
CC
L
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
8
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
CDIP
CDIP
CDIP
CDIP
CDIP
PDIP
Drawing
CD54HC540F3A
CD54HC541F
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
J
J
20
20
20
20
20
20
1
1
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
CD54HC541F3A
CD54HCT541F
CD54HCT541F3A
CD74HC540E
J
1
J
1
J
1
N
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC540M
CD74HC540M96
CD74HC541E
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
DW
DW
N
20
20
20
20
20
20
20
20
20
20
20
20
20
20
25
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC541M
SOIC
SOIC
TSSOP
TSSOP
SSOP
PDIP
DW
DW
PW
PW
DB
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
CD74HC541M96
CD74HC541PW
CD74HC541PWR
CD74HC541SM
CD74HCT540E
CD74HCT540M
CD74HCT540M96
CD74HCT541E
CD74HCT541M
CD74HCT541M96
2000
70
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
20
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SOIC
SOIC
PDIP
DW
DW
N
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
2000
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SOIC
SOIC
DW
DW
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明