CD74HC597M [TI]
High Speed CMOS Logic 8-Bit Shift Register with Input Storage; 具有输入存储的高速CMOS逻辑8位移位寄存器
| 型号： | CD74HC597M |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High Speed CMOS Logic 8-Bit Shift Register with Input Storage |
| 文件： | 总10页 (文件大小：51K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD74HC597,
CD74HCT597
Data sheet acquired from Harris Semiconductor
SCHS191
High Speed CMOS Logic
8-Bit Shift Register with Input Storage
January 1998
Features
Description
• Buffered Inputs
The Harris CD74HC597 and CD74HCT597 are high-speed
silicon gate CMOS devices that are pin-compatible with the
LSTTL 597 devices. Each device consists of an 8-flip-flop
input register and an 8-bit parallel-in/serial-in, serial-out shift
register. Each register is controlled by its own clock. A “low” on
the parallel load input (PL) shifts parallel stored data asyn-
chronously into the shift register. A “low” master input (MR)
• Asynchronous Parallel Load
[ /Title
(CD74
HC597
,
o
• Typical f
MAX
= 60MHz at V = 5V, C = 15pF, T = 25 C
CC L A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
CD74
HCT59
7)
/Sub-
ject
(High
Speed
CMOS
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads clears the shift register. Serial input data can also be synchro-
nously shifted through the shift register when PL is high.
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
PKG.
NO.
o
PART NUMBER TEMP. RANGE ( C) PACKAGE
• HC Types
CD74HC597E
CD74HCT597E
CD74HC597M
CD74HCT597M
NOTES:
-55 to 125
-55 to 125
-55 to 125
-55 to 125
16 Ld PDIP
16 Ld PDIP
E16.3
E16.3
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
16 Ld SOIC M16.15
16 Ld SOIC M16.15
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
Pinout
CD74HC597, CD74HCT597
(PDIP, SOIC)
TOP VIEW
D1
D2
1
2
3
4
5
6
7
8
16 V
CC
15 D0
14 D
D3
S
D4
13 PL
12 ST
D5
CP
D6
11 SH
CP
10 MR
Q7
D7
9
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1915.1
Copyright © Harris Corporation 1998
1
CD74HC597, CD74HCT597
Functional Diagram
DS
14
15
D0
1
D1
2
D2
3
PARALLEL
DATA
D3
D4
D5
D6
D7
8-BIT
SHIFT
REG.
8 F/F
STORAGE
REG.
4
5
INPUTS
6
7
9
Q7
12
ST
CP
11
13
10
SH
CP
PL
MR
FUNCTION TABLE
MR
ST
CP
SH
PL
X
L
FUNCTION
CP
↑
X
X
H
H
L
Data Loaded to Input Flip-Flops
↑
X
X
X
Data Loaded from Inputs to Shift Register
Data Transferred from Input Flip-Flops to Shift Register
No Clock Edge
X
L
L
Invalid Logic, State of Shift Register Indeterminate when
Signals Removed
X
X
X
H
H
L
Shift Register Cleared
↑
H
Shift Register Clocked Qn = Qn-1, Q0 = D
S
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High CP Level
2
CD74HC597, CD74HCT597
Absolute Maximum Ratings
Thermal Information
o
DC Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3)
θ
( C/W)
CC
DC Input Diode Current, I
JA
IK
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
For V < -0.5V or V > V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
OK
For V < -0.5V or V > V
I
I
CC
160
o
DC Output Diode Current, I
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
O
O
CC
o
DC Drain Current, per Output, I
O
For -0.5V < V < V
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
O
CC
(SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, I
O
For V > -0.5V or V < V
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
O
O
CC
DC V
or Ground Current, I
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
CC
CC
Operating Conditions
o
o
Temperature Range, T . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
A
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V
I
O
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
TEST
CONDITIONS
o
o
o
o
o
25 C
TYP
-40 C TO 85 C -55 C TO 125 C
V
(V)
CC
PARAMETER
HC TYPES
SYMBOL
V (V)
I
I
(mA)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
O
High Level Input
Voltage
V
-
-
-
2
4.5
6
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
-
1.5
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
IH
3.15
-
-
3.15
-
-
3.15
4.2
4.2
4.2
-
Low Level Input
Voltage
V
-
2
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
-
0.5
1.35
1.8
-
IL
4.5
6
-
-
-
-
-
-
High Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
-0.02
2
1.9
1.9
1.9
OH
-0.02
-0.02
-
4.5
6
4.4
-
4.4
-
4.4
-
5.9
-
5.9
-
5.9
-
High Level Output
Voltage
TTL Loads
-
-
-
-
-
-
-
-4
4.5
6
3.98
-
3.84
-
3.7
-
-5.2
0.02
0.02
0.02
-
5.48
-
5.34
-
5.2
-
Low Level Output
Voltage
CMOS Loads
V
V
or V
IH IL
2
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
-
-
-
-
-
-
-
0.1
0.1
0.1
-
OL
4.5
6
Low Level Output
Voltage
TTL Loads
-
4
4.5
6
0.26
0.26
±0.1
0.33
0.33
±1
0.4
0.4
±1
5.2
-
Input Leakage
Current
I
V
or
6
I
CC
GND
3
CD74HC597, CD74HCT597
DC Electrical Specifications (Continued)
TEST
CONDITIONS
o
o
o
o
o
25 C
-40 C TO 85 C -55 C TO 125 C
V
CC
PARAMETER
SYMBOL
V (V)
I
(mA)
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
I
O
Quiescent Device
Current
I
V
GND
or
0
6
-
-
8
-
80
-
160
µA
CC
CC
HCT TYPES
High Level Input
Voltage
V
-
-
-
-
4.5 to
5.5
2
-
-
-
-
-
0.8
-
2
-
-
0.8
-
2
-
-
0.8
-
V
V
V
IH
Low Level Input
Voltage
V
4.5 to
5.5
IL
High Level Output
Voltage
CMOS Loads
V
V
V
or V
-0.02
4.5
4.5
4.5
4.5
4.4
4.4
4.4
OH
IH
IH
IL
High Level Output
Voltage
TTL Loads
-4
3.98
-
-
-
-
3.84
-
3.7
-
V
V
V
Low Level Output
Voltage
CMOS Loads
V
or V
0.02
4
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
OL
IL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
V
and
0
0
-
5.5
5.5
-
-
-
±0.1
8
-
-
-
±1
80
-
-
-
±1
µA
µA
µA
I
CC
GND
Quiescent Device
Current
I
V
or
-
160
490
CC
CC
GND
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆I
V
4.5 to
5.5
100
360
450
CC
CC
-2.1
HCT Input Loading Table
INPUT
UNIT LOADS
D
0.2
0.3
1.5
1.5
S
D
n
PL, MR
ST , SH
CP CP
NOTE: Unit load is ∆I
CC
Table, e.g., 360µA max. at 25 C.
limit specified in DC Electrical Specifications
o
Prerequisite for Switching Specifications
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V) MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
HC TYPES
SH Frequency
f
2
6
-
-
-
-
-
-
5
-
-
-
-
-
-
4
-
-
-
-
-
-
MHz
MHz
MHz
CP
MAX
4.5
6
30
35
25
29
20
23
4
CD74HC597, CD74HCT597
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V) MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
SH
Pulse Width
Pulse Width
t
t
t
t
2
80
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
20
17
75
15
13
100
20
17
90
18
15
125
25
21
65
13
11
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
120
24
20
90
18
15
120
24
20
105
21
18
150
30
26
75
15
13
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CP
W
W
W
W
4.5
6
16
14
60
12
10
80
16
14
70
14
12
100
20
17
50
10
9
ST
2
CP
4.5
6
MR Pulse Width
PL Pulse Width
2
4.5
6
2
4.5
6
ST
CP
Time
to SH
Setup
t
t
2
CP
SU
SU
4.5
6
D
D
to SH
to ST
Setup Time
Setup Time
2
S
n
CP
CP
4.5
6
ST
CP
Time
to SH
Setup
t
t
2
0
CP
H
H
4.5
6
0
0
0
0
0
0
D
D
to SH
to ST
Hold Time
Hold Time
2
3
3
3
S
n
CP
CP
4.5
6
3
3
3
3
3
3
MR to SH
Time
Removal
t
2
3
3
3
CP
REM
4.5
6
3
3
3
3
3
3
HCT TYPES
SH
Frequency
f
4.5
4.5
4.5
4.5
4.5
4.5
25
20
13
18
16
24
-
-
-
-
-
-
-
-
-
-
-
-
20
25
16
23
20
30
-
-
-
-
-
-
-
-
-
-
-
-
16
30
20
27
24
36
-
-
-
-
-
-
-
-
-
-
-
-
MHz
ns
CP
CP
CP
MAX
SH
Pulse Width
Pulse Width
t
t
t
t
W
W
W
W
ST
ns
MR Pulse Width
PL Pulse Width
ns
ns
ST
CP
to SH
Setup
t
ns
CP
SU
Time
5
CD74HC597, CD74HCT597
Prerequisite for Switching Specifications (Continued)
o
o
o
o
o
25 C
TYP
-
-40 C TO 85 C
-55 C TO 125 C
PARAMETER
SYMBOL
V
(V) MIN
MAX
MIN
TYP
MAX
MIN
TYP
MAX UNITS
CC
D
D
to SH
to ST
Setup Time
Setup Time
t
4.5
10
-
13
-
-
15
-
-
ns
S
n
CP
CP
H
ST to SH Hold Time
CP CP
t
t
4.5
4.5
0
3
-
-
-
-
0
3
-
-
-
-
0
3
-
-
-
-
ns
ns
H
D
D
to SH
CP
Hold Time
Hold Time
S
H
to ST
n
CP
MR to SH
Time
Removal
t
4.5
10
-
-
13
-
-
15
-
-
ns
CP
REM
Switching Specifications Input t , t = 6ns
r
f
o
o
o
o
o
25 C
TYP MAX
-40 C to 85 C -55 C to 125 C
TEST
PARAMETER
HC TYPES
Propagation Delay
SH to Q7
SYMBOL CONDITIONS
V
(V) MIN
MIN
MAX
MIN
MAX UNITS
CC
t
t
t
t
t
C = 50pF
2
-
-
175
35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
220
44
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
265
53
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
PLH, PHL
L
4.5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CP
C =15pF
14
L
C = 50pF
6
-
30
200
40
-
37
250
50
-
45
300
60
-
L
PL to Q7
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C =15pF
17
L
C = 50pF
6
-
34
240
48
-
43
300
60
-
51
360
72
-
L
ST
CP
to Q7
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C =15pF
20
L
C = 50pF
6
-
41
175
35
-
51
220
44
-
61
265
53
-
L
MR to Q7
t
C = 50pF
2
-
PLH, PHL
L
4.5
5
-
C =15pF
14
L
C = 50pF
6
-
30
75
15
13
10
-
37
95
19
16
10
-
45
110
22
19
10
-
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
2
-
L
4.5
6
-
-
-
C
C = 50pF
L
-
I
Power Dissipation
C
-
5
13.5
PD
Capacitance, (Notes 4, 5)
HCT
Propagation Delay
t
t
PLH, PHL
SH
CP
to Q7
C = 50pF
4.5
5
-
-
-
-
-
-
-
16
-
38
-
-
-
48
-
-
-
57
-
ns
ns
ns
ns
ns
ns
L
C = 15pF
L
PL to Q7
t
t
t
C = 50pF
4.5
5
48
-
60
-
72
-
PLH, PHL
L
C = 15pF
20
-
-
-
-
-
L
ST
CP
to Q7
t
C = 50pF
4.5
5
56
-
70
-
84
-
PLH, PHL
L
C = 15pF
23
L
6
CD74HC597, CD74HCT597
Switching Specifications Input t , t = 6ns (Continued)
r
f
o
o
o
o
o
25 C
-40 C to 85 C -55 C to 125 C
TEST
PARAMETER
MR to Q7
SYMBOL CONDITIONS
V
(V) MIN
TYP MAX
MIN
MAX
55
-
MIN
MAX UNITS
CC
t
t
C = 50pF
4.5
5
-
-
-
-
-
-
18
-
44
-
-
-
-
-
-
-
-
-
-
-
66
-
ns
ns
ns
pF
pF
PLH, PHL
L
C = 15pF
L
Output Transition Time
Input Capacitance
t
, t
TLH THL
C = 50pF
4.5
-
15
10
-
19
10
-
22
10
-
L
C
C = 50pF
L
-
I
Power Dissipation
C
-
5
18.5
PD
Capacitance, (Notes 4, 5)
NOTES:
4. C
PD
is used to determine the dynamic power consumption, per package.
2
2
5. P = C
V
f + Σ (C V
CC
f ) where: f = Input Frequency, f = Output Frequency, C = Output Load Capacitance, V
= Supply
D
PD CC
i
L
o
i
o
L
CC
Voltage.
Test Circuits and Waveforms
I
t
+ t =
WH
WL
I
t C = 6ns
fC
r
L
t
+ t
=
L
WL
WH
t C = 6ns
t C
f
L
fC
t C
f
L
L
r
L
3V
V
CC
90%
10%
2.7V
0.3V
CLOCK
CLOCK
50%
10%
1.3V
0.3V
50%
t
50%
1.3V
t
1.3V
GND
GND
t
t
WH
WL
WH
WL
NOTE: Outputs should be switching from 10% V
to 90% V
in
NOTE: Outputs should be switching from 10% V
to 90% V
in
CC
CC
CC
CC
accordance with device truth table. For f
, input duty cycle = 50%. accordance with device truth table. For f , input duty cycle = 50%.
MAX
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t = 6ns
t = 6ns
t = 6ns
t = 6ns
r
f
r
f
V
3V
CC
90%
50%
10%
2.7V
1.3V
0.3V
INPUT
INPUT
GND
GND
t
t
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
50%
10%
INVERTING
OUTPUT
INVERTING
OUTPUT
10%
t
t
PLH
PHL
t
t
PLH
PHL
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
7
CD74HC597, CD74HCT597
Test Circuits and Waveforms (Continued)
t C
t C
t C
t C
r
L
f
L
f
L
r
L
V
3V
CC
90%
10%
2.7V
0.3V
CLOCK
INPUT
CLOCK
INPUT
50%
1.3V
GND
GND
t
t
t
t
H(L)
H(H)
H(H)
H(L)
V
3V
CC
DATA
INPUT
DATA
INPUT
50%
1.3V
t
SU(L)
1.3V
1.3V
GND
GND
t
t
t
SU(H)
SU(H)
SU(L)
t
t
90%
50%
t
t
THL
TLH
THL
TLH
90%
1.3V
90%
90%
1.3V
OUTPUT
OUTPUT
10%
10%
t
t
t
PLH
t
PHL
PHL
PLH
t
REM
t
REM
V
3V
CC
SET, RESET
OR PRESET
SET, RESET
OR PRESET
50%
1.3V
GND
GND
IC
IC
C
C
L
L
50pF
50pF
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
8
CD74HC597, CD74HCT597
Timing Diagram
SHIFT CLOCK
SH
CP
SERIAL DATE
D
S
MASTER RESET
MR
PARALLEL LOAD
PL
STORAGE CLOCK
ST
CP
L
D0
L
H
L
D1
D2
D3
D4
D5
D6
D7
Q7
L
L
L
L
H
L
L
L
L
PARALLEL
DATA
INPUTS
H
H
L
H
L
L
H
L
H
H
L
H
L
H
L
H
H
L
H
L
H
L
H
L
L
L
H
L
H
H
RESET
SHIFT
REGISTER
SERIAL
SHIFT
SERIAL
SHIFT
SERIAL
SHIFT
SERIAL
SHIFT
LOAD
FLIP-FLOPS
PARALLEL LOAD
SHIFT REGISTER
LOAD
FLIP-FLOPS
PARALLEL LOAD
SHIFT REGISTER
PARALLEL LOAD FLIP-FLOPS
AND SHIFT REGISTER
9
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