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CD74HC73 [TI]

Dual J-K Flip-Flop with Reset Negative-Edge Trigger; 双JK触发器与复位负边沿触发
CD74HC73
型号： CD74HC73
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Dual J-K Flip-Flop with Reset Negative-Edge Trigger
双JK触发器与复位负边沿触发

触发器
文件： 总8页 (文件大小：59K)
中文：  中文翻译
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CD74HC73,  
CD74HCT73  
Data sheet acquired from Harris Semiconductor  
SCHS134  
Dual J-K Flip-Flop with Reset  
Negative-Edge Trigger  
February 1998  
Features  
Description  
• Hysteresis on Clock Inputs for Improved Noise  
Immunity and Increased Input Rise and Fall Times  
The Harris CD74HC73 and CD74HCT73 utilize silicon gate  
CMOS technology to achieve operating speeds equivalent to  
LSTTL parts. They exhibit the low power consumption of  
standard CMOS integrated circuits, together with the ability  
to drive 10 LSTTL loads.  
[ /Title  
(CD74  
HC73,  
CD74  
HCT73  
)
• Asynchronous Reset  
• Complementary Outputs  
• Buffered Inputs  
These flip-flops have independent J, K, Reset and Clock  
inputs and Q and Q outputs. They change state on the  
negative-going transition of the clock pulse. Reset is  
accomplished asynchronously by a low level input. This  
device is functionally identical to the HC/HCT107 but differs  
in terminal assignment and in some parametric limits.  
• Typical f  
MAX  
= 60MHz at V = 5V, C = 15pF,  
CC L  
o
T = 25 C  
A
/Sub-  
ject  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
(Dual  
J-K  
Flip-  
Flop  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads The 74HCT logic family is functionally as well as pin  
compatible with the standard 74LS logic family.  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
Ordering Information  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
TEMP. RANGE  
PKG.  
NO.  
o
PART NUMBER  
CD74HC73E  
CD74HCT73E  
CD74HC73M  
NOTES:  
( C)  
PACKAGE  
14 Ld PDIP  
14 Ld PDIP  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
E14.3  
• HC Types  
- 2V to 6V Operation  
E14.3  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
M14.15  
at V  
= 5V  
CC  
• HCT Types  
6. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
7. Wafer and die for this part number is available which meets all  
electrical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
IL  
IH  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
OL OH  
l
Pinout  
CD74HC73, CD74HCT73  
(PDIP, SOIC)  
TOP VIEW  
1CP  
1R  
1
2
3
4
5
6
7
14 1J  
13 1Q  
12 1Q  
11 GND  
10 2K  
1K  
V
CC  
2CP  
2R  
9
8
2Q  
2Q  
2J  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1721.1  
Copyright © Harris Corporation 1998  
1
CD74HC73, CD74HCT73  
Functional Diagram  
14  
12  
1J  
1Q  
3
FF 1  
13  
1K  
1Q  
1
2
1CP  
1R  
7
10  
5
9
8
2J  
2K  
2Q  
2Q  
FF 2  
2CP  
GND = 11  
= 4  
6
2R  
V
CC  
TRUTH TABLE  
INPUTS  
OUTPUTS  
R
L
CP  
X
↓
J
X
L
K
Q
Q
X
L
L
H
H
H
H
H
H
No Change  
↓
H
L
L
H
L
L
↓
H
H
X
H
↓
H
X
Toggle  
H
No Change  
NOTE:  
H =High Level (Steady State)  
L
X
=Low Level (Steady State)  
= Irrelevant  
↓
= High-to-Low Transition  
Logic Diagram  
14 (7)  
3(10)  
J
12 (9)  
Q
J
K
K
CL  
CL  
1 (5)  
2 (6)  
13 (8)  
Q
A  
CP  
R
R
2
CD74HC73, CD74HCT73  
Absolute Maximum Ratings  
Thermal Information  
o
DC Supply Voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V  
Thermal Resistance (Typical, Note 3)  
θ
( C/W)  
CC  
DC Input Diode Current, I  
For V < -0.5V or V > V  
JA  
IK  
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
90  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA  
I
I
CC  
175  
o
DC Drain Current, per Output, I  
O
Maximum Junction Temperature (Hermetic Package or Die) . . . 175 C  
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150 C  
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C  
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300 C  
o
For -0.5V < V < V  
+ 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA  
O
CC  
o
o
DC Output Diode Current, I  
OK  
For V < -0.5V or V > V  
o
+ 0.5V . . . . . . . . . . . . . . . . . . . .±20mA  
O
O
CC  
DC Output Source or Sink Current per Output Pin, I  
O
(SOIC - Lead Tips Only)  
For V > -0.5V or V < V  
+ 0.5V . . . . . . . . . . . . . . . . . . . .±25mA  
O
O
CC  
DC V  
or Ground Current, I  
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA  
CC  
CC  
Operating Conditions  
o
o
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
A
Supply Voltage Range, V  
CC  
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V  
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V  
DC Input or Output Voltage, V , V . . . . . . . . . . . . . . . . . 0V to V  
I
O
CC  
Input Rise and Fall Time  
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)  
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)  
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation  
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
8. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
DC Electrical Specifications  
TEST  
CONDITIONS  
o
o
o
o
o
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
HC TYPES  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
High Level Input  
Voltage  
V
-
-
-
2
1.5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5  
-
1.5  
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA  
IH  
4.5  
3.15  
-
-
3.15  
-
-
3.15  
6
2
4.2  
4.2  
4.2  
-
Low Level Input  
Voltage  
V
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
-
0.5  
1.35  
1.8  
-
IL  
4.5  
6
-
-
-
-
-
-
High Level Output  
Voltage  
CMOS Loads  
V
V
or  
-0.02  
2
1.9  
1.9  
1.9  
OH  
IH  
V
IL  
-0.02  
-0.02  
-
4.5  
6
4.4  
-
4.4  
-
4.4  
-
5.9  
-
5.9  
-
5.9  
-
High Level Output  
Voltage  
TTL Loads  
-
-
-
-
-
-
-
-4  
4.5  
6
3.98  
-
3.84  
-
3.7  
-
-5.2  
0.02  
0.02  
0.02  
-
5.48  
-
5.34  
-
5.2  
-
Low Level Output  
Voltage  
CMOS Loads  
V
V
or  
2
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
-
-
-
-
-
-
-
0.1  
0.1  
0.1  
-
OL  
IH  
V
IL  
4.5  
6
Low Level Output  
Voltage  
TTL Loads  
-
4
4.5  
6
0.26  
0.26  
±0.1  
0.33  
0.33  
±1  
0.4  
0.4  
±1  
5.2  
-
Input Leakage  
Current  
I
V
or  
6
I
CC  
GND  
3
CD74HC73, CD74HCT73  
DC Electrical Specifications (Continued)  
TEST  
o
o
o
o
o
CONDITIONS  
25 C  
-40 C TO 85 C  
-55 C TO 125 C  
PARAMETER  
SYMBOL V (V)  
I
(mA)  
V
(V) MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
I
O
CC  
Quiescent Device  
Current  
I
V
GND  
or  
0
6
-
-
4
-
40  
-
80  
µA  
CC  
CC  
HCT TYPES  
High Level Input  
Voltage  
V
-
-
-
-
-
4.5 to  
5.5  
2
-
-
-
-
-
0.8  
-
2
-
-
0.8  
-
2
-
-
0.8  
-
V
V
V
IH  
Low Level Input  
Voltage  
V
4.5 to  
5.5  
IL  
High Level Output  
Voltage  
V
V
or  
IH  
4.5  
4.4  
4.4  
4.4  
OH  
V
IL  
CMOS Loads  
High Level Output  
Voltage  
-0.02  
4.5  
3.98  
-
-
3.84  
-
3.7  
-
V
TTL Loads  
Low Level Output  
Voltage CMOS Loads  
V
V
V
or  
IH  
-4  
4.5  
4.5  
-
-
-
-
0.1  
-
-
0.1  
-
-
0.1  
0.4  
V
V
OL  
IL  
Low Level Output  
Voltage  
TTL Loads  
0.02  
4
0.26  
0.33  
Input Leakage  
Current  
I
V
and  
GND  
5.5  
5.5  
-
±0.1  
-
±1  
-
±1  
µA  
I
CC  
Quiescent Device  
Current  
I
V
or  
0
-
-
-
-
4
-
-
40  
-
-
80  
µA  
µA  
CC  
CC  
GND  
Additional Quiescent  
Device Current Per  
Input Pin: 1 Unit Load  
∆I  
CC  
V
4.5 to  
5.5  
100  
360  
450  
490  
CC  
- 2.1  
NOTE:  
9. For dual-supply systems theoretical worst case (V = 2.4V, V  
I
= 5.5V) specification is 1.8mA.  
CC  
HCT Input Loading Table  
HC TYPES  
HCT TYPES  
3V  
INPUT  
All  
UNIT LOADS  
Input Level  
V
0.3  
CC  
V
S
50% V  
CC  
1.3V  
NOTE: Unit Load is ∆I  
tions table, e.g., 360µA max at 25 C.  
limit specified in DC Electrical Specifica-  
CC  
o
NOTE: Transition times and propagation delay times.  
Prerequisite For Switching Specifications  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
CP Pulse Width  
t
t
-C = 50pF  
2
80  
16  
14  
80  
16  
14  
-
-
-
-
-
-
-
-
-
-
-
-
100  
20  
-
-
-
-
-
-
120  
24  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
w
L
4.5  
6
17  
20  
R Pulse Width  
-C = 50pF  
2
100  
20  
120  
24  
w
L
4.5  
6
17  
20  
4
CD74HC73, CD74HCT73  
Prerequisite For Switching Specifications (Continued)  
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
100  
20  
17  
3
MAX  
MIN  
120  
24  
20  
3
MAX  
UNITS  
ns  
Setup Time, J, K to CP  
t
C = 50pF  
2
4.5  
6
80  
16  
14  
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SU  
L
ns  
-
ns  
Hold Time, J, K to CP  
Removal Time  
t
C = 50pF  
2
-
ns  
H
L
4.5  
6
3
-
3
3
ns  
3
-
3
3
ns  
t
-C = 50pF  
2
80  
16  
14  
6
-
100  
20  
17  
5
120  
24  
20  
4
ns  
REM  
L
4.5  
6
-
ns  
-
ns  
CP Frequency  
f
C = 50pF  
2
-
MHz  
MHz  
MHz  
MHz  
MAX  
L
4.5  
5
30  
-
-
25  
-
20  
-
C = 15pF  
60  
-
L
C = 50pF  
6
35  
29  
23  
L
HCT TYPES  
CP Pulse Width  
t
t
C = 50pF  
L
4.5  
4.5  
4.5  
4.5  
4.5  
4.5  
5
16  
18  
16  
3
-
-
-
-
-
-
-
-
-
20  
23  
20  
3
-
-
-
-
-
-
-
24  
27  
24  
3
-
-
-
-
-
-
-
ns  
ns  
w
R Pulse Width  
CL = 50pF  
CL = 50pF  
CL = 50pF  
CL = 50pF  
CL = 50pF  
CL = 15pF  
w
Setup Time, J, K to CP  
Hold Time, J, K to CP  
Removal Time  
t
-
ns  
SU  
t
-
ns  
H
t
12  
30  
-
-
15  
25  
-
18  
20  
-
ns  
REM  
CP Frequency  
f
-
MHz  
MHz  
MAX  
60  
Switching Specifications Input t , t = 6ns  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
HC TYPES  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
MIN  
MAX  
UNITS  
Propagation Delay,  
CP to Q  
t
t
t
, t  
C = 50pF  
L
2
4.5  
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
160  
32  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200  
40  
-
-
-
240  
48  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
PLH PHL  
CL = 15pF  
13  
-
-
C = 50pF  
6
28  
160  
32  
-
34  
200  
40  
-
-
41  
240  
48  
-
L
Propagation Delay,  
CP to Q  
, t  
PLH PHL  
C = 50pF  
2
-
-
L
4.5  
5
-
-
C = 15pF  
13  
-
-
L
C = 50pF  
6
28  
145  
29  
-
34  
180  
36  
-
-
41  
220  
44  
-
L
Propagation Delay,  
R to Q, Q  
, t  
PLH PHL  
C = 50pF  
2
-
-
L
4.5  
5
-
-
C = 15pF  
12  
-
-
L
C = 50pF  
6
25  
75  
15  
13  
31  
95  
19  
16  
-
38  
110  
22  
19  
L
Output Transition Time  
t
, t  
TLH THL  
C = 50pF  
2
-
18  
-
L
4.5  
6
-
-
-
5
CD74HC73, CD74HCT73  
Switching Specifications Input t , t = 6ns (Continued)  
r
f
o
o
o
o
o
25 C  
-40 C TO 85 C -55 C TO 125 C  
TEST  
V
CC  
PARAMETER  
Input Capacitance  
SYMBOL CONDITIONS (V)  
MIN TYP MAX  
MIN  
MAX  
10  
-
MIN  
MAX  
10  
-
UNITS  
pF  
C
-
-
-
-
-
-
10  
-
-
-
-
-
I
Power Dissipation Capacitance  
(Notes 5, 6)  
C
5
28  
pF  
PD  
HCT TYPES  
Propagation Delay,  
CP to Q  
t
t
t
, t  
C = 50pF  
L
4.5  
4.5  
4.5  
-
-
-
-
-
-
38  
36  
34  
-
-
-
48  
45  
43  
-
-
-
57  
54  
51  
ns  
ns  
ns  
PLH PHL  
Propagation Delay,  
CP to Q  
, t  
PLH PHL  
CL = 50pF  
CL = 50pF  
Propagation Delay,  
R to Q, Q  
, t  
PLH PHL  
Output Transition Time  
Input Capacitance  
t
, t  
TLH THL  
C = 50pF  
L
4.5  
-
-
-
-
-
-
15  
10  
-
-
-
-
19  
10  
-
-
-
-
22  
10  
-
ns  
pF  
pF  
C
-
-
I
Power Dissipation Capacitance  
(Notes 5, 6)  
C
5
28  
PD  
NOTES:  
10. C  
is used to determine the dynamic power consumption, per flip-flop.  
PD  
11. P = C  
2
2
V
f + Σ C V  
f where f = input frequency, f = output frequency, C = output load capacitance, V  
= supply voltage.  
D
PD CC  
i
L
CC  
o
i
o
L
CC  
Test Circuits and Waveforms  
I
t
+ t =  
WH  
WL  
I
t C = 6ns  
fC  
r
L
t
+ t  
=
L
WL  
WH  
t C = 6ns  
t C  
f
L
f
t C  
f
L
CL  
r
L
3V  
V
CC  
90%  
10%  
2.7V  
CLOCK  
CLOCK  
50%  
10%  
1.3V  
0.3V  
50%  
t
50%  
1.3V  
t
1.3V  
0.3V  
GND  
GND  
t
t
WH  
WL  
WH  
WL  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
NOTE: Outputs should be switching from 10% V  
to 90% V  
in  
CC  
CC  
CC  
CC  
accordance with device truth table. For f  
, input duty cycle = 50%.  
accordance with device truth table. For f  
, input duty cycle = 50%.  
MAX  
MAX  
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND  
PULSE WIDTH  
t = 6ns  
t = 6ns  
t = 6ns  
t = 6ns  
r
f
r
f
V
3V  
CC  
90%  
50%  
10%  
2.7V  
1.3V  
0.3V  
INPUT  
INPUT  
GND  
GND  
t
t
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
50%  
10%  
INVERTING  
OUTPUT  
INVERTING  
OUTPUT  
10%  
t
t
PLH  
PHL  
t
t
PLH  
PHL  
FIGURE 4. HC AND HCU TRANSITION TIMES AND PROPAGA-  
TION DELAY TIMES, COMBINATION LOGIC  
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION  
DELAY TIMES, COMBINATION LOGIC  
6
CD74HC73, CD74HCT73  
Test Circuits and Waveforms (Continued)  
t C  
t C  
t C  
t C  
r
L
f
L
f
L
r
L
V
3V  
CC  
90%  
10%  
2.7V  
0.3V  
CLOCK  
INPUT  
CLOCK  
INPUT  
50%  
1.3V  
GND  
GND  
t
t
t
t
H(L)  
H(H)  
H(H)  
H(L)  
V
3V  
CC  
DATA  
INPUT  
DATA  
INPUT  
50%  
1.3V  
t
SU(L)  
1.3V  
1.3V  
GND  
GND  
t
t
t
SU(H)  
SU(H)  
SU(L)  
t
t
90%  
50%  
t
t
THL  
TLH  
THL  
TLH  
90%  
1.3V  
90%  
90%  
1.3V  
OUTPUT  
OUTPUT  
10%  
10%  
t
t
t
PLH  
t
PHL  
PHL  
PLH  
t
REM  
t
REM  
V
3V  
CC  
SET, RESET  
OR PRESET  
SET, RESET  
OR PRESET  
50%  
1.3V  
GND  
GND  
IC  
IC  
C
C
L
L
50pF  
50pF  
FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,  
AND PROPAGATION DELAY TIMES FOR EDGE  
TRIGGERED SEQUENTIAL LOGIC CIRCUITS  
7
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pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
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safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
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Copyright 1998, Texas Instruments Incorporated  

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